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12-bit, 65 msps if to baseband diversity receiver ad6652 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features snr = 90 db in 150 k hz band width (to ny qu ist @ 61. 44 msps) worst harmonic = 83 dbc (to nyquist @ 61.4 4 msps) integrated dual-channel adc: sample rates up to 65 msps if sampling fre q uencies to 20 0 mhz internal ad c voltage referenc e integrated adc sample-an d -hold inputs flexible analog input range (1 v to 2 v p-p) differentia l an alog inputs adc clock du ty cy cle stabilizer 85 db channel i s olation/crosstalk integrated wideband digital downc o nverter (ddc): crossbar switched ddc input s digital res a mpling for noninteger decimation programmable decimating fi r filters flexible control for multicarri er and phase d array dual ag c stag es for output l e vel control dual 16-bit par a llel or 8-bit lin k output ports user-configura ble built-in self -test (bist) cap a bility energy-saving power-down modes applic ati o ns communications diversit y ra dio systems multimode digital recei v ers: gsm, edge, phs, amps, umts , wcdma, cdm a -one, is95, is136, cd ma2000, imt-2 000 i/q demodulati on systems smart antenna systems general-purpo s e software ra dios b r o a dband dat a applicatio ns instrumentation and test eq ui pment func tio n a l block di agram / / / / / 12 12 channel a channel b lia lia lib lib otra otrb pseudo random noise sequence synca syncb syncc syncd aclk v ina + v in a ? v inb+ v inb? v ref s ense refta refba reftb refbb pdwn shrdref dutyen rcf outputs channels 0, 1, 2, 3 rcf outputs channels 0, 1, 2, 3 to output ports to output ports to output ports to output ports dual-channel 12-bit a/d front end wideband digital downconverter (ddc) channel 0 channel 1 channel 2 channel 3 +3.0avdd +3.3vddio 2.5vdd agnd dgnd clk data cont add port a control output mux circuitry control port b 8-bit dsp link or 16-bit parallel output 8-bit dsp link or 16-bit parallel output *data interleaving and interpolating hb filter ram coef. filter ram coef. filter ram coef. filter ram coef. filter nco nco nco nco inp u t matrix rcic2 resampler cic5 rcic2 resampler cic5 rcic2 resampler cic5 rcic2 resampler cic5 vref adc channel a adc channel b sha sha mode select clock duty cycle stabilizer external sync. circuit ddc clk built-in self-test circuitry program microport 83 3 agc a* agc b* 03198- 0- 001 fi g u r e 1 .
ad6652 rev. 0 | page 2 of 76 table of contents product description......................................................................... 4 product highlights ....................................................................... 4 specifications..................................................................................... 5 recommended operating conditions ...................................... 5 adc dc specifications............................................................... 5 adc switching specifications.................................................... 5 adc ac specifications ............................................................... 6 electrical characteristics ............................................................. 7 general timing characteristics ................................................. 8 microprocessor port timing characteristics ........................... 9 absolute maximum ratings.......................................................... 10 thermal characteristics ............................................................ 10 test level ..................................................................................... 10 esd caution................................................................................ 10 pin configuration and function descriptions........................... 11 typical performance characteristics ........................................... 14 ddc timing diagrams ................................................................. 17 terminology .................................................................................... 23 adc equivalent circuits........................................................... 23 theory of operation ...................................................................... 24 adc architecture ...................................................................... 24 digital downconverter architecture overview ......................... 29 data input matrix....................................................................... 29 numerically controlled oscillator........................................... 29 second-order rcic filter ......................................................... 29 fifth-order cic filter ............................................................... 29 ram coefficient filter .............................................................. 29 interpolating half-band filters and agc............................... 29 control register and memory map address notation ............. 31 ddc input matrix...................................................................... 31 ddc data latency ..................................................................... 31 gain switching............................................................................ 31 numerically controlled oscillator............................................... 33 frequency translation to baseband......................................... 33 nco shadow register ............................................................... 33 nco frequency hold-off register......................................... 33 phase offset................................................................................. 33 nco control register ............................................................... 33 second-order rcic filter ............................................................. 35 rcic2 scale factor ..................................................................... 35 rcic2 output level ................................................................... 36 rcic2 rejection.......................................................................... 36 decimation and interpolation registers ................................. 36 rcic2 scale register .................................................................. 36 fifth-order cic filter ................................................................... 37 cic5 rejection ........................................................................... 37 ram coefficient filter .................................................................. 38 rcf decimation register.......................................................... 38 rcf decimation phase.............................................................. 38 rcf filter length....................................................................... 38 rcf output scale factor and control register ..................... 39 interpolating half-band filters .................................................... 40 automatic gain control................................................................ 41 agc loop ................................................................................... 41 desired signal level mode........................................................ 41 synchronization.......................................................................... 44 user-configurable built-in self-test (bist) .............................. 45 ram bist ................................................................................... 45 channel bist.............................................................................. 45 channel/chip synchronization.................................................... 46 start .............................................................................................. 46 hop............................................................................................... 48
ad6652 rev. 0 | page 3 of 76 parallel output ports.......................................................................50 channel mode .............................................................................50 agc mode ...................................................................................51 master/slave pclk modes ........................................................52 parallel port pin functions ........................................................52 link port...........................................................................................53 link port data format ...............................................................53 link port timing.........................................................................53 tigersharc configuration ......................................................54 external memory map ...................................................................55 access control register (acr) .................................................56 channel address register (car) .............................................56 soft_sync control register........................................................56 pin_sync control register.........................................................57 sleep control register................................................................57 data address registers...............................................................57 channel address registers (car)............................................57 input port control registers .....................................................63 output port control registers ..................................................64 microport control ......................................................................71 applications .....................................................................................73 ad6652 receiver applications..................................................73 design guidelines .......................................................................73 ad6652 evaluation board and software .....................................75 outline dimensions........................................................................76 ordering guide ...........................................................................76 revision history 7/04revision 0: initial version
ad6652 rev. 0 | page 4 of 76 product description the ad6652 is a mixed-signal if to baseband receiver consisting of dual 12-bit 65 msps adcs and a wideband multimode digital downconverter (ddc). the ad6652 is designed to support communications applications where low cost, small size, and versatility are desired. the ad6652 is also suitable for other applications in imaging, medical ultrasound, instrumentation, and test equipment. the dual adc core features a multistage differential pipelined architecture with integrated output error correction logic. both adcs feature wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer is provided to compen- sate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. adc data outputs are internally connected directly to the receivers digital downconverter (ddc) input matrix, simplify- ing layout and reducing interconnection parasitics. overrange bits are provided for each adc channel to alert the user to adc clipping. level indicator bits are also provided for each ddc input port that can be used for external digital vga control. the digital receiver has four reconfigurable channels and provides extraordinary processing flexibility. the receiver input matrix routes the adc data to individual channels, or to all four receive processing channels. each receive channel has five cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (nco)), two fixed-coefficient decimating filters (cic), a programmable ram coefficient decimating fir filter (rcf), and an interpolating half-band filter/agc stage. following the cic filters, one, several, or all channels can be configured to use one, several, or all the rcf filters. this permits the processing power of four 160-tap rcf fir filters to be combined or used individually. after fir filtering, data can be routed directly to the two external 16-bit output ports. alternatively, data can be routed through two additional half-band interpolation stages, where up to four channels can be combin ed (interleaved), interpolated, and processed by an automatic gain control (agc) circuit with 96 db range. the outputs from the two agc stages are also routed directly to the two external 16-bit output ports. each output port has a 16-bit parallel output and an 8-bit link port to permit seamless data interface with dsp devices such as the ts-101 tigersharc? dsp. a multiplexer for each port selects one of six data sources to appear on the device outputs pins. the ad6652 is part of the analog devices softcell? multimode and multicarrier transceiver chipset. the softcell receiver digitizes a wide spectrum of if frequencies and then down- converts the desired signals to baseband using individual channel ncos. the ad6652 provides user-configurable digital filters for removal of undesired baseband components, and the data is then passed on to an external dsp, where demodulation and other signal processing tasks are performed to complete the information retrieval process. each receive channel is independ- ently configurable to provide simultaneous reception of the carrier to which it is tuned. this if sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. high dynamic range decimation filters offer a wide range of decimation rates. the ram-based architecture allows easy reconfiguration for multimode applications. the decimating filters remove unwanted signals and noise from the channel of interest. when the channel occupies less bandwidth than the input signal, this rejection of out-of-band noise is referred to as processing gain . by using large decimation factors, this process- ing gain can improve the snr of the adc by 20 db or more. in addition, the programmable ram coefficient filter allows antialiasing, matched filtering, and static equalization functions to be combined in a single, cost-effective filter. flexible power-down options allow significant power savings, when desired. product highlights ? integrated dual 12-bit 65 msps adc. ? integrated wideband digital downconverter (ddc). ? proprietary, differential sha input maintains excellent snr performance for input frequencies up to 200 mhz. ? crossbar-switched digital downconverter input ports. ? digital resampling permits noninteger relationships between the adc clock and the digital output data rate. ? energy-saving power-down modes. ? 32-bit ncos with selectable amplitude and phase dithering for better than ?100 dbc spurious performance. ? cic filters with user-programmable decimation and interpolation factors. ? 160-tap ram coefficient filter for each ddc channel. ? dual 16-bit parallel output ports and dual 8-bit link ports. ? 8-bit microport for register programming, register read- back, and coefficient memory programming.
ad6652 rev. 0 | page 5 of 76 specifications recommended operating conditions table 1. parameter temp test level min typ max unit avdd full iv 2.75 3.0 3.3 v vdd full iv 2.25 2.5 2.75 v vddio full iv 3.0 3.3 3.6 v t ambient iv ?40 +25 +85 c adc dc specifications avdd = 3.0 v, vdd = 2.5 v, vddio = 3.3 v, 61.44 msps, ?1.0 dbfs differential input, 1.0 v internal reference, unless otherwise noted. table 2. parameter (conditions) temp test level min typ max unit resolution full iv 12 bits internal voltage reference output voltage error (1 v mode) full iv 5 35 mv load regulation @ 1.0 ma full v 0.8 mv output voltage error (0.5 v mode) full v 2.5 mv load regulation @ 0.5 ma full v 0.1 mv input referred noise input span = 1 v internal 25c v 0.54 lsb rms input span = 2 v internal 25c v 0.27 lsb rms analog input input span = 1.0 v full iv 1 v p-p input span = 2.0 v full iv 2 v p-p input capacitance full v 7 pf reference input resistance full v 7 k? matching characteristics offset error full v 0.1 % fsr gain error full v 0.1 % fsr adc switching specifications avdd = 3.0 v, vdd = 2.5 v, vddio = 3.3 v, 61.44 msps, ?1.0 dbfs differential input, 1.0 v internal reference, unless otherwise noted. table 3. parameter (conditions) temp test level min typ max unit switching performance maximum conversion rate full iv 65 msps minimum conversion rate full v 1 msps aclk period full v 15.4 ns aclk pulse width high 1 full v 6.2 aclk/2 ns aclk pulse width low 1 full v 6.2 aclk/2 ns data output parameters wake-up time 2 full v 2.5 ms out-of-range recovery time full v 2 cycles 1 duty cycle stabilizer enabled. 2 wake-up time is dependent on the value of decoupling capacitors, typical values shown with 0.1 f and 10 f capacitors on reft and refb.
ad6652 rev. 0 | page 6 of 76 adc ac specifications avdd = 3.0 v, vdd = 2.5 v, vddio = 3.3 v, 61.44 msps, ?1.0 dbfs differential input, 1.0 v internal reference. table 4. parameter (conditions) temp test level min typ max unit signal-to-noise ratio 1 (without harmonics) analog input frequency 10.4 mhz 25c v 90 db full v 90 db 25.0 mhz 25c ii 85 90 db full v 90 db 68.0 mhz 25c ii 84 89.5 db full v 88.5 db 101 mhz 25c v 88.0 db 150 mhz 25c v 87.5 db 200 mhz 25c v 85 db worst harmonic (2 nd or 3 rd ) 1 analog input frequency 10.4 mhz 25c v ?85 dbc full v ?83 dbc 25 mhz 25c ii ?83 ?71 dbc full v ?80 dbc 68 mhz 25c ii ?80 dbc full v ?76 dbc 101 mhz 25c v ?79 dbc 150 mhz 25c v ?72 dbc 200 mhz 25c v ?69 dbc two-tone imd rejection (two tones separated by 1 mhz) 2 analog inputs = 15/16 mhz 25c v ?81 dbc analog inputs = 55/56 mhz 25c v ?79 dbc channel isolation/crosstalk 3 full v 85 db 1 analog input a or b = single tone @ ?1 db below full scale, 150 khz ddc filter bandwidth. 2 analog input a or b = each single tone @ ? 7 db below full scale, 5 mhz ddc filter bandwidth. 3 analog inputs a and b = each single tone @ ? 1 db below full scale at 4.3 mhz and 68 mhz, 150 khz ddc filter bandwidth.
ad6652 rev. 0 | page 7 of 76 electrical characteristics avdd = 3.0 v, vdd = 2.5 v, vddio = 3.3 v, 61.44 msps, ?1.0 dbfs differential input, 1.0 v internal reference, unless otherwise noted. table 5. parameter (conditions) temp test level min typ max unit logic inputs logic compatibility full iv 3.3 v cmos logic 1 voltage full iv 2.0 v logic 0 voltage full iv 0.8 v logic 1 current full iv ?10 +10 a logic 0 current full iv ?10 +10 a input capacitance 25c v 4 pf logic outputs logic compatibility full iv 3.3 v cmos/ttl logic 1 voltage (v oh ) (i oh = 0.25 ma) full iv 2.4 vddio ? 0.2 v logic 0 voltage (v ol ) (i ol = 0.25 ma) full iv 0.2 0.4 v supply currents narrow band (150 khz bw) (61.44 mhz clk) four individual channels i avdd 25c ii 160 200 215 ma i vdd 25c ii 240 280 300 ma i vddio 25c ii 25 40 45 ma cdma (1.25mhz bw) (61.44 mhz clk) example 1 i avdd 25c v 200 ma i vdd 25c v 336 ma i vddio 25c v 68 ma wcdma (5 mhz bw) (61.44 mhz clk) example 1 i avdd 25c v 200 ma i vdd 25c v 330 ma i vddio 25c v 89 ma total power dissipation narrow band (150 khz bw) (61.44 mhz clk) four individual channels 25c ii 1.2 1.5 1.6 w cdma (61.44 mhz) 1 25c v 1.7 w wcdma (61.44 mhz) 1 25c v 1.7 w adc in standby and ddc in sleep mode 2 25c v 2.3 mw 1 all signal processing stages and all ddc channels active. 2 adc standby power measured with aclk inactive.
ad6652 rev. 0 | page 8 of 76 general timing characteristics all timing specifications valid over vdd range of 2.25 v to 2.75 v and vddio range of 3.0 v to 3.6 v. cload = 40 pf on all outputs, unless otherwise specified. table 6. parameter (conditions) temp test level min typ max unit clk timing requirements t clk clk period full iv 15.4 ns t clkl clk width low full iv 6.2 t clk /2 ns t clkh clk width high full iv 6.2 t clk /2 ns reset timing requirements t resl reset width low full iv 30.0 ns level indicator output switching characteristics t dli clk to li (lia, lia ; lib, lib ) output delay time full iv 3.3 10.0 ns sync timing requirements t ss sync(a,b,c,d) to clk setup time full iv 2.0 ns t hs sync(a,b,c,d) to clk hold time full iv 1.0 ns parallel port timing requirements (master mode) switching characteristics 1 t dpoclkl clk to pclk delay (divide-by-1) full iv 6.5 10.5 ns t dpoclkll clk to pclk delay (divide-by-2, -4, or -8) full iv 8.3 14.6 ns t dpreq pclk to pxreq delay 1.0 ns t dpp pclk to px[15:0] delay 0.0 ns input characteristics t spa pxack to pclk setup time 7.0 ns t hpa pxack to pclk hold time ?3.0 ns parallel port timing requirements (slave mode) switching characteristics 1 t poclk pclk period full iv 12.5 ns t poclkl pclk low period (when pclk divisor = 1) full iv 2.0 0.5 t poclk ns t poclkh pclk high period (when pclk divisor = 1) full iv 2.0 0.5 t poclk ns t dpreq pclk to pxreq delay 10.0 ns t dpp pclk to px[15:0] delay 11.0 ns input characteristics t spa pxack to pclk setup time iv 1.0 ns t hpa pxack to pclk hold time iv 1.0 ns link port timing requirements switching characteristics 1 t rdlclk pclk to lxclkout delay full iv 2.5 ns t fdlclk pclk to lxclkout delay full iv 0 ns t rlclkdat lclkout to lx[7:0] delay full iv 0 2.9 ns t flclkdat lclkout to lx[7:0] delay full iv 0 2.2 ns 1 the timing parameters for px[15:0], pxreq, and pxac k apply for port a and b (x stands for a or b).
ad6652 rev. 0 | page 9 of 76 microprocessor port timing characteristics all timing specifications valid over vdd range of 2.25 v to 2.75 v and vddio range of 3.0 v to 3.6 v. cload = 40 pf on all outputs, unless otherwise specified. table 7. microprocessor port, mode inm (mode = 0) temp test level min typ max unit mode inm write timing t sc control 1 to clk setup time full iv 2.0 ns t hc control 1 to clk hold time full iv 2.5 ns t hwr wr (r/ w ) to rdy( dtack ) hold time full iv 7.0 ns t sam address/data to wr (r/ w ) setup time full iv 3.0 ns t ham address/data to rdy( dtack ) hold time full iv 5.0 ns t drdy wr (r/ w ) to rdy( dtack ) delay full iv 8.0 ns t acc wr (r/ w ) to rdy( dtack ) high delay full iv 4 t clk 5 t clk 9 t clk ns mode inm read timing t sc control 1 to clk setup time full iv 5.0 ns t hc control 1 to clk hold time full iv 2.0 ns t sam address to rd ( ds ) setup time full iv 0.0 ns t ham address to data hold time full iv 5.0 ns t drdy rd ( ds ) to rdy( dtack ) delay full iv 8.0 ns t acc rd ( ds ) to rdy( dtack ) high delay full iv 8 t clk 10 t clk 13 t clk ns microprocessor port, mode mnm (mode = 1) temp test level min typ max unit mode mnm write timing t sc control 1 to clk setup time full iv 2.0 ns t hc control 1 to clk hold time full iv 2.5 ns t hds ds ( rd ) to dtack (rdy) hold time full iv 8.0 ns t hrw r/ w ( wr ) to dtack (rdy) hold time full iv 7.0 ns t sam address/data to r/ w ( wr ) setup time full iv 3.0 ns t ham address/data to r/ w ( wr ) hold time full iv 5.0 ns t ddtack ds ( rd ) to dtack (rdy) delay full iv 8.0 ns t acc r/ w ( wr ) to dtack (rdy) low delay full iv 4 t clk 5 t clk 9 t clk ns mode mnm read timing t sc control 1 to clk setup time full iv 5.0 ns t hc control 1 to clk hold time full iv 2.0 ns t hds ds ( rd ) to dtack (rdy) hold time full iv 8.0 ns t sam address to ds ( rd ) setup time full iv 0.0 ns t ham address to data hold time full iv 5.0 ns t ddtack ds ( rd ) to dtack (rdy) delay full iv 8.0 ns t acc ds ( rd ) to dtack (rdy) low delay full iv 8 t clk 10 t clk 13 t clk ns 1 specification pertains to control signals: r/w, ( wr ), ds , ( rd ), and cs .
ad6652 rev. 0 | page 10 of 76 absolute maximum ra tings table 8. p a r a m e t e r r a t i n g electr i c a l avdd voltage ?0.3 v to +3.9 v vdd voltage ?0.3 v to +2.75 v vddio voltage ?0.3 v to +3.9 v agnd, dgnd ?0.3 v to +0.3 v adc vina, vinb analog input voltage ?0.3 v to avdd + 0.3 v adc digital input voltage ?0.3 v to avdd + 0.3 v a d c ot ra , ot rb d i g i t a l ou tpu t vol t ag e ?0.3 v to vddio + 0.3 v adc vref, refa , refb input volt age ?0.3 v to avdd + 0.3 v ddc digital input voltage ?0.3 v to vddio + 0.3 v ddc digital output voltage ?0.3 v to vddio + 0.3 v environ m en t a l operating tem p erature range (ambient) ?40c to +85c maximum junction temperature under bias 150c storage temperature range (a mbient) ?65c to +150c s t r e s s es a b o v e t h os e lis t e d u n de r t h e a b s o l u t e m a xim u m r a tin g s m a y ca use pe rm a n en t d a ma g e t o t h e devi ce . t h is i s a st re ss r a t i n g on l y ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . thermal c h ar a c teristics 256-lead cs p b ga, 17 mm s q . ja = 23c/w , s t il l a i r . est i m a te b a s e d o n jedec jc51 -2 m o del usin g h o r i zo n t a l ly pos i ti o n ed 4- la y e r boa r d . test le vel i. 100% production tested. ii. 100% production tested at 25 c. iii. sample tes ted only. iv. parameter g u ara n teed by design and characterization testing. v. parameter is a ty pical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing for in dustrial tem pera tur e range. esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad6652 rev. 0 | page 11 of 76 pin configuration and fu nction descriptions table 9. bga pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a dgnd pa7_la7 a2 pa6_la6 d1 d3 cs reset mode syncd otra pdwn avdd avdd agnd agnd b do not connect pa4_la4 pach0_ laclk out a0 dgnd r/ w ( wr ) d4 d6 syncc synca lia dutyen avdd avdd agnd agnd c pa9 pa3_la3 a1 ds ( rd ) d0 d2 d5 d7 dtack (rdy) syncb lia lib avdd avdd agnd vin+b d pa1_la1 pa2_la2 pach1_ laclkin vdd vdd vdd vdd vddio vddio vddio vddio vddio avdd avdd agnd vin?b e pa8 pa5_la5 n.c. vdd vdd vdd vdd vddio vddio vddio vddio vddio avdd avdd agnd agnd f pa0_la0 dgnd pa10 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd agnd g pa12 pa11 pa13 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd refbb reftb h pareq pa15 pa14 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd sense j chip_id1 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd vref k chip_id3 paack chip_id0 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd refba refta l pb6_lb6 pb7_lb7 dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd vddio avdd agnd agnd agnd m chip_id2 pb3_lb3 pb4_lb4 vddio vddio vddio vddio vdd vdd vdd vdd vddio avdd avdd agnd agnd n paiq pbch1_ lbclk in pb2_lb2 vddio vddio vddio vddio vdd vdd vdd vdd vddio avdd avdd agnd vin?a p dgnd pb0_lb0 pb8 pb10 pb14 vddio pback lib n.c. n.c. otrb n.c. avdd avdd agnd vin+a r pbiq pbch0_l bclkout pb1_ lb1 pb9 pb12 pb15 n.c. n.c. n.c. n.c. n.c. pdwn avdd avdd agnd agnd t dgnd pclk pb5_ lb5 pb11 pb13 pbreq n.c. n.c. n.c. n.c. dclk shrdref avdd aclk agnd agnd
ad6652 rev. 0 | page 12 of 76 table 10. pin function descriptions pin no. mnemonic type function power supply a13, b13, c13, d13, e13, f13, g13, h13, j13, k13, l13, m13, n13, p13, r13, t13, a14, b14, c14, d14, e14, m14, n14, p14, r14 avdd power 3.0 v analog supply, 25 pins. d4, d5, d6, d7, e4, e5, e6, e7, m8, m9, m10, m11, n8, n9 , n10, n11 vdd power 2.5 v di gital core supply, 16 pins. d8, d9, d10, d11, d12, e8, e9, e10, e11, e12, f12, g12, h12, j12, k12, l12, m4, m5, m6, m7, m12, n4, n5, n6, n7, n12, p6 vddio power 3.3 v digital i/o supply, 27 pins. a1, b5, f2, f4, f5, f6, f7, f8, f9, f10, f11, g4, g5, g6, g7, g8, g9, g10, g11, h4, h5, h6, h7, h8, h9, h10, h11, j2, j3, j4, j5, j6, j7, j8, j9, j10, j11, k4, k5, k6, k7, k8, k9, k10, k11, l3, l4, l5, l6, l7, l8, l9, l10, l11, p1, t1 dgnd ground digital ground, 56 pins. a15, a16, b15, b16, c15, d15, e15, e16, f14, f15, f16, g14, h14, h15, j14, j15, k14, l14, l15, l16, m15, m16, n15, p15, r15, r16, t15, t16 agnd ground analog ground, 28 pins. miscellaneous e3, p9, p10, p12, r7, r8, r9, r10, r11, t7, t8, t9, t10 nc n/a no connect, 13 pins. b1 dnc n/a do not connect. pin no. mnemonic type function adc inputs p16 vin+a input differential analog input pin (+) for channel a. n16 vin?a input differential analog input pin (?) for channel a. c16 vin+b input differential analog input pin (+) for channel b. d16 vin?b input differential analog input pin (?) for channel b. j16 vref i/o voltage reference input/output. h16 sense input voltage reference mode select. t14 aclk input adc master clock. b12 dutyen input duty cycl e stabilizer, active high. a12, r12 pdwn 1 input power-down enable, active high. t12 shrdref input shared voltage reference select, low = independent, high = shared. adc outputs a11 otra output out-of-range indicato r for channel a, high = overrange. p11 otrb output out-of-ran ge indicator for channel b, high = overrange. k16 refta output top reference voltage, channel a. g16 reftb output top reference voltage, channel b. k15 refba output bottom refere nce voltage, channel a. g15 refbb output bottom reference voltage, channel b. ddc inputs a8 reset input master reset, active low. t11 dclk input ddc master clock. t2 pclk i/o link port clock output or parallel port clock input. d3 pach1_laclkin 2 i/o channel id output bit, msb, for parallel port a, or link port a data ready input. function depends on logic state of 0x 1b:7 of output port control register. n2 pbch1_lbclkin 2 i/o channel id output bit, msb, for parallel port b, or link port b data ready input. function depends on logic state of 0x1d:7 of output port control register. b10 synca 3 input hardware sync, pin a, ro uted to all receiver channels. c10 syncb 3 input hardware sync, pin b, ro uted to all receiver channels. b9 syncc 3 input hardware sync, pin c, ro uted to all receiver channels. a10 syncd 3 input hardware sync, pin d, ro uted to all receiver channels. k3, j1, m1, k1 chip_id[3:0] 3 input chip id selector, four pins, used in co njunction with access control register bits 5C2.
ad6652 rev. 0 | page 13 of 76 pin no. mnemonic type function ddc outputs b11 lia output level indica tor, input a, data a. c11 lia output level indicator, input a, data a . c12 lib output level indica tor, input b, data b. p8 lib output level indicator, input b, data b . b3 pach0_laclkout 2 output channel id output bit, lsb, for parallel port a, or link port a clock output. function depends on logic state of 0x 1b:7 of output port control register. r2 pach0_lbclkout 2 output channel id output bit, lsb, for parallel po rt b, or link port b clock output. function depends on logic state of 0x1d:7 of output port control register. f1, d1, d2, c2, b2, e2, a4, a2 pa[7:0]_la[7:0] output link port a data or parallel port a data [7:0], eight pins. p2, r3, n3, m2, m3, t3, l1, l2 pb[7:0_lb[7:0] output link port b data or parallel port b data [7:0], eight pins. e1, c1, f3, g2, g1, g3, h3, h2 pa[15:8] output parallel port a data [15:8], eight pins. p3, r4, p4, t4, r5, t5, p5, r6 pb[15:8] output parallel port b data [15:8], eight pins. n1 paiq output parallel port a i or q data indicator, i = high, q = low. r1 pbiq output parallel port b i or q data indicator, i = high, q = low. parallel output port control k2 paack input parallel port a acknowledge. h1 pareq output parallel port a request. p7 pback input parallel port b acknowledge. t6 pbreq output parallel port b request. microport control c5, a5, c6, a6, b7, c7, b8, c8 d[7:0] i/o bidirectional microport data, eight pins . this bus is three-stated when cs is high. b4, c3, a3 a[2:0] input microport address bus, 3 pins. c4 ds ( rd ) 4 input function depends upon mode pin. active low data strobe when mode = 1. active low read strobe when mode = 0. c9 dtack (rdy) 4 , 5 output function depends upon mode pin. active low data acknowledge when mode = 1. microport status pin when mode = 0. b6 r/ w ( wr ) 4 input read/write strobe when mode = 1. active low write strobe when mode = 0. a9 mode 4 input mode select pin. 0 = intel mode, 1 = motorola mode. a7 cs 3 input active low chip select. logic 1 th ree-states the microport data bus. 1 pdwn pins must be the same logic level: both logic high or both logic low. 2 pach0 and pach1 form a 2-bit output word in the parallel output mode that identifies the processing channel (0, 1, 2, or 3) wh ose data appears on port a parallel outputs. likewise, pbch0 and pbch1 identify the channel for port b. 3 pins with a pull-down resistor of nominal 70 k?. 4 mode 0 is intel nonmultiplexed (imn), and mode 1 is motorola nonmultiplexed (mnm). pin logic level corresponds to mode. 5 pins with a pull-up resistor of nominal 70 k?.
ad6652 rev. 0 | page 14 of 76 typical perf orm ance cha r acte ristics ?150 ?140 ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?1 10 ?70 ?50 ?30 ?90 dbfs ?300 ?200 ?100 0 100 200 300 frequency (khz) 03198-0-060 a in = ? 1dbfs snr = 90db (200khz bw) 32k fft f i gure 2. gsm / edg e with s i ngle t o ne a in = 3 0 m h z; e n c o de = 6 1 .4 4 ms ps ?150 ?140 ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?1 10 ?70 ?50 ?30 ?90 dbfs ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 frequency (mhz) 03198-0-062 a in = ? 1dbfs snr = 80db (1.25mhz bw) 32k fft f i gure 3. cdma 20 0 0 w i th si ngle t o ne a in = 7 6 m h z; e n c o de = 6 1 .4 4 ms ps ?150 ?140 ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?1 10 ?70 ? ?30 ?90 dbfs ? 1 01 23 4 ?3 ? 2 ?4 frequency (mhz) 03198-0-064 5 0 a in = ? 1dbfs snr = 70db (5mhz bw) 32k fft ?150 ?140 ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?1 10 ?70 ?50 ?30 ?90 dbfs ?300 ?200 ?100 0 100 200 300 frequency (khz) 03198-0-059 32k fft f i gure 5. gsm / e d g e carr ie r a in = 3 0 m h z; e n code = 61 .4 4 msps ?150 ?140 ?130 ?120 ?100 ?60 ?40 ? 2 0 ?10 0 ?80 ?1 10 ?70 ?50 ?30 ?90 dbfs ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 frequency (mhz) 03198-0-061 32k fft f i gure 6. cdma 20 0 0 ca rr ier a in = 7 6 m h z; e n code = 61 .4 4 msps ?150 ?140 ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?1 10 ?70 ?50 ?30 ?90 dbfs ? 1 01 23 4 ?3 ? 2 ?4 frequency (mhz) 03198-0-063 32k fft f i gure 7. wc dma carr ie r a in = 169 mh z ; enc o de = 61 .4 4 msp s f i gure 4. wc dma with s i ngle t o ne a in = 16 9 mh z ; enc o de = 61 .44 msp s
ad6652 rev. 0 | page 15 of 76 ?150 ?140 ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?1 10 ?70 ?50 ?30 ?90 dbfs ? 1 01 23 4 ?3 ? 2 ?4 frequency (mhz) 03198-0-070 encode = 61.44msps a in = ? 7dbfs 32k fft f i gure 8. t w o t o ne s at 1 5 m h z and 16 mh z 40 50 60 70 80 90 100 sn r ( d b ) [ 150kh z b w ] ?4 0 ? 3 0 ?60 ? 50 ? 2 0 ? 10 0 analog input amplitude (dbfs) 03198-0-071 snr f i g u re 9. n o is e v s . a n al og a m p lit ude at 2 5 m h z 40 50 60 70 80 90 100 harmonics (dbc ) ?4 0 ? 3 0 ?60 ? 50 ? 2 0 ? 10 0 analog input amplitude (dbfs) 03198-0-073 harmonics harmonics = 80db reference line f i g u re 10. h a r m o n i c s v s . a n alog a m pl i t ude at 25 m h z ?150 ?140 ?130 ?120 ?100 ?60 ?40 ?20 ?10 0 ?80 ?1 10 ?70 ?50 ?30 ?90 dbfs ? 1 01 23 4 ?3 ? 2 ?4 frequency (mhz) 03198-0-066 encode = 61.44msps a in = ? 7dbfs 32k fft f i g z u re 11. t w o t o n e s at 55 m h z and 5 6 m h 40 50 60 70 80 90 100 sn r ( d b ) [ 150kh z b w ] ?4 0 ? 3 0 ?60 ? 50 ? 2 0 ? 10 0 analog input amplitude (dbfs) 03198-0-072 snr f i g u re 12. no is e v s . a n al og a m p lit ude at 6 8 m h z 40 50 60 70 80 90 100 harmonics (dbc ) ?4 0 ? 3 0 ?60 ? 50 ? 2 0 ? 10 0 analog input amplitude (dbfs) 03198-0-074 harmonics harmonics = 80db reference line f i g u re 13. h a r m o n i c s v s . a n alog a m pl i t ude at 68 m h z
ad6652 rev. 0 | page 16 of 76 86 90 88 92 sn r ( d b ) [ b w z] 0 1 0 2 03 0 4 0 5 06 0 7 0 analog input frequency (mhz) 03198-0-068 25c 85c ?40 c a in = ? 1dbfs f i g u re 14. no is e v s . a n al og f r eque nc y = 150kh 65 70 75 80 85 90 wors t-cas e harmonic (dbc ) 75 100 125 150 175 200 25 50 0 analog frequency (mhz) 03198-0-069 25c a in = ? 1dbfs f i g u re 15. h a r m o n i c s v s . a n alog f r equ e nc y 84 86 88 90 92 sn r ( d b ) [ b w = 150kh z] 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 analog input frequency (mhz) 03198-0-067 25 c a in = ? 1dbfs f i g u re 16. no is e v s . a n al og f r eque nc y (if)
ad6652 rev. 0 | page 17 of 76 ddc timi ng diagrams lia, lib lia, lib cl k t dli t clkh t clkl t clk 03198-0-065 f i g u re 17. l e vel ind i c a to r o u t p ut swi t c h ing ch ar ac t e r i s t ic s reset t resl 03198-0-003 f i gur e 1 8 . re se t tim i ng re quir em ents t hs t ss clk synca syncb syncc syncd 03198-0-006 f i g u re 19. sync ti ming input s clk pcl k t dpoclkl 03198-0-007 f i g u re 20. pcl k t o clk swi t ch ing ch a r ac t e r i s t ics d i v i d e - b y-1 clk pclk t dpoclkll t poclkl t poclkh 03198-0-008 f i g u re 21. pcl k t o clk swi t ch ing ch a r ac t e r i s t ics d i v i d e - b y-2, -4, o r -8
ad6652 rev. 0 | page 18 of 76 pclk pxack t spa t hpa 03198-0-009 f i g u re 22. m a s t e r m o de px a c k to pc lk s e t u p a n d h o ld char ac t e ris t i c s data 1 data 2 data n ? 1 data n pclk pxreq pxack px[15:0] t spa t dpp t spa t dpp 03198-0-010 f i g u re 23. m a s t e r m o de px a c k to pc lk swi t ch ing ch ar ac te ris t i c s pclk data 1 data n t dpp t dpp t dpreq pxack pxreq px[15:0] 03198-0-011 f i g u re 24. m a s t e r m o de px r e q to pc lk swi t ch ing ch ar ac te ris t i c s t spa t hpa t poclkl t poclkh pclk pxac k 03198-0-012 f i g u re 25. sl ave m o de px a c k t o pclk s e t u p and h o ld cha r ac t e r i s t ics
ad6652 rev. 0 | page 19 of 76 data 1 data 2 data n ? 1 data n pclk pxreq pxack px[15:0] t spa t dpp t spa t dpp 03198-0-013 f i g u re 26. sl ave m o de px a c k t o pclk switc h ing c h a r ac ter i s t ics pclk data 1 data n t dpp t dpp t dpreq pxack pxreq px[15:0] 03198-0-014 f i g u re 27. sl ave m o de px r e q t o pcl k switc h ing c h a r ac ter i s t ics pclk lxclkout t rdlclk t fdlcl 03198-0-015 f i gure 28. lxclk o ut t o pclk s w it ch ing char acteristics
ad6652 rev. 0 | page 20 of 76 lxclkout lxclkin lx[7:0] wait 6 cycles one time connectivity check next transfer acknowledge next transfer begins 8 lxclkout cycles d0 d1 f i gure 29. lxclk i n t o l x c l d2 d3 d4 d15 d3 03198-0-016 k o ut d a t a w it ch ing ch ar acteristics d0 d1 d2 s t fdlclkdat t rdlclkdat 03198-0-017 [ 7 : 0 ] d a ta s w it ch ing ch ar acteristics lxclkout lx[7:0] f i gure 30. lxclk o ut t o l x clk rd (ds) wr (r/w) cs l i d d a t a notes 1. t acc access time depends on the address accessed. access time is measured from fe of wr to re of rdy. 2. t acc requires a maximum of 9 clk periods. a[2:0] d[7:0] v a l i d a d d r e s s v a rdy (dtack) t sc t hc t hwr t ham t sam t ham t sam t drdy t acc 03198-0-018 f i gure 31. inm m i cropo r t w r i t e t i m i ng r e qui r e m ents
ad6652 rev. 0 | page 21 of 76 t sc clk rd (ds) wr (rw) s o n t h e a d d r e s s c l k p e r i o d t sam a[2:0] d[7:0] rdy (dtack) notes 1. t acc a c c e s s t i m e d e p e n d from fe of wr to re of rdy. 2. t acc r e q u i r e s a m a x i m u m o f 1 3 cs a c c e s s e d . a c c e s s t i m e i s m e a s u r e d s . t h c valid address t ha valid data t drdy t acc 03198-0-019 i ming r e quirem ents f i gure 32. inm m i cropo r t r e a d t v a l i d a d d r e s s valid data clk ds (rd) rw (wr) t h e a d d r e s s e s s t i m e i s m e a s u r e d h e f e o f d t a c k . x i m u m o f 9 c l k p e r i o d s . cs a[2:0] d[7:0] dtack (rdy) notes 1. t acc a c c e s s t i m e d e p e n d s o n f r o m f e o f d s t o t 2. t acc r e q u i r e s a m a a c c e s s e d . a c c t sc t hc t hds t hrw t ham t acc t sam t h a m t sam t ddtack 03198-0-020 o r t w r i t e t i m i ng r e qui r e m ents f i gure 33. mnm m i c r o p
ad6652 rev. 0 | page 22 of 76 clk ds (rd) r/w (wr) a[2:0] d[7:0] dtack (rdy) t sc t acc t ddtack notes 1. t acc a c c e s s t i m e d e p e n d s o n t f r o m t h e f e o f d s t o t h e f e o 2. t acc r e q u i r e s a m a x i m u m o f 1 3 h e a d d r e s s a c c f d t a c k . c l k p e r i o d e s s e d . a c c e s s t i m e i s m e a s u r e d s . valid address valid data t sam t hc t hds 03198-0-021 t ha cs t i m i n g requi r em ents f i gure 3 4 . mnm m i cro p or t rea d
ad6652 rev. 0 | page 23 of 76 a l e u ist zon e s and a l i a s o n to i t s e lf. if s a m y t h e b a n d wi d t h o f t h e i n p u t h a (s am ple-and- h o ld am plif i e r) a n d clo c k j i t t e r . ( j i t t e r adds g (o v e rsa m p r s wh en t h e c y co m p o n en t s o lo w th i s t f r eq uen c y (f cl o g i n p e sa m p le d u t- o f -r a n ge r e co v e r y t i m e ou t - o f - r a n ge r e co v e r y ti m e i s th tim e i t ta k e s f o r th e a n alog- to - d i g i t a l c o af te r a t r a n sien t f r o o v e n e g a ti ve f u l l s c a l e , o r f r o m 10% be lo w n e g a ti v e f u l l s c ale t o 10% b e l o w p o s i t i ve f u l l s c a l e. pr o c e s s i ng g a i n w h en t h e t u n e d cha n ne l o c c u p i es les s b a n d wi d t h t h an t h e in p u t sig n a l , t h i s r e j e c t io n o f o u t-o f -b and n o is e is r e fer r e d t o as pr oce s sing g a in . by usin g la rge de cima t i o n fac t ors, t h is p r o c ess- in g ga i n can i m p r o v e t h e snr o f t h e a d c b y 20 db o r m o r e . the fol l o w in g e q ua t i o n ca n b e us e d t o es t i ma te p r o c es sin g ga i n : terminology cr o s s t alk c o upl i ng on to one ch an nel b e i n g d r ive n by a ( ? 0 . 5 d b f s ) s i g n a l w h en t h e ad jac e n t i n t e r f er in g cha n n e l is dr i v e n b y a f u l l -s c sig n al . m e as ur em en t in c l udes a l l s p urs r e s u l t ing f r o m bo th dir e c t co u p li n g a nd m i x i n g com p on e n ts. i f s a mpl i ng ( u nd er s a mpl i ng ) d u e to t h e ef fe c t s o f a l iasing, a n ad c is n o t ne c e ss a r i l y l i m i te d to n y qu i s t s a m p l i ng . f r e q u e nc i e s ab ove n y qu i s t are a l i a s e d a n d a p p e a r in t h e f i rst n y q u ist zone (dc t o sa m p le r a t e /2). c a r e m u st b e t a k e n to limi t t h e b a ndwi d t h o f t h e s a m p le d sig n a l s o t h a t i t do es n o t o v erla p n y q p ling p e r f o r ma nce is lim i te d b s m o r e noi s e a t h i g h e r i n put f r e q u e nc i e s . ) n y q u is t s a m p li n l in g) o v e r sa m p l i n g o c c u f r eq ue n f t h e a n alog i n p u t si g n al a r e b e e n y q u c k / 2 ) , a n d r e q u i r e s tha t th e a n a l o u t f r eq ue n c y b a t le a s t tw o s a m p les p e r c y cle . o e n v e r te r ( a d c ) to re a c qu i r e t h e an a l o g i n put m 1 0 % ab o v e p o si t i v e f u l l s c ale t o 1 0 % ab ? ? ? ? ? ? = bandwidth filter rate sample _gain processing _ 2 _ log 10 s i g n a l -t o-n o is e r a ti o (s nr) t h e ra ti o o f th e rm s v a l u e o f th e m e as u r ed in p u t s i gn al t o th e rm s s u m o f all o t h e r s p ectral co m p o n en t s wi th in th e p r o- g r a m m e d d d c f i l t er b a ndwi d t h, excl udin g t h e f i rst six ha r m o n ics cib e ls ( d b) . tw o - t o n e i m d r e j e c t i o n the ra t i o o f t h e r m s val u e o f ei t h er i n p u t t o n e to t h e r m s val u e o f th e w o r s t th i r d - o r d e r in t e rm od ula t i o n p r od u c t ; r e po r t ed in db c. a n d dc. the val u e for s n r is exp r ess e d i n de adc equ i v a lent circ uit s avdd 03198-0-022 f i gure 35. a n a l og i n put circuit avdd 03198-0-023 f i gure 3 6 . di g i ta l input vdd 03198-0-024 f i gure 3 7 . di g i ta l o u tput
ad6652 rev. 0 | page 24 of 76 n e nd n ? 2 interpolation and channel interleave ront cf stages to achieve demanding filtering objectives that are not possible with just one channel. in the following sections, each st ge is examined to allow the user to f the dual adc design is useful for diversity reception of signals, where the adcs are operating identically on the same carrier but from two separate antennae. the adcs can also be operated with independent analog inputs. the user can sample any fs/2 frequency segment from dc to 100 mhz using appropriate low-pass or band-pass filtering at the adc inputs with little loss in adc performance. operation to 200 mhz analog input is permitted, but at the expense of increased adc distortion. in nondiversity applications, up to four gsm/edge-type carriers can be concurrently processed from the adc stage. wideband signals, such as wcdma/cdma2000, require the power of two ad6652 processing channels per carrier to adequately remove adjacent channel interference. when diversity techniques a er of carriers that can be processed is halv ocessing require- ment of diversity reception. ble channel multiplexing in the digital downconverter dc) stage allows one to four channels to be interleaved onto ronization input pins allow startup, ated re the ad6652 front-end consists of two high performance, 12-bit adcs, preceded by differential sample-and-hold amplifiers (sha) that provide excellent snr performance from dc to 200 mhz. a flexible, integrated voltage reference allows analog inputs up to 2 v p-p. each channel is equipped with an overrange pin that toggles high whenever the analog input exceeds the upper or lower reference voltage boundary. adc outputs are internally routed to the input matrix of the ddc stage for channel distribution. the adc data outputs are not directly accessible to the user. each sample-and-hold amplifier (sha) is followed by a pipe- lined switched capacitor adc. the pipelined adc is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on the preceding samples. sampling occurs on the rising edge of the clock. analog input operation the analog inputs to the ad6652 are differential switched capacitor shas that have been designed for optimum perform- ance while processing differential input signals. the ad6652 accepts inputs over a wide common-mode range; however, an input common-mode voltage v cm , one-half of avdd, is recommended to maintain optimal performance and to minimize signal-dependent errors. referring to figure 38, the clock signal alternatively switches the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adcs input; therefore, the precise values are dependent upon the application. in if undersampling applications, any shunt capaci- tors should be removed. in combination with the driving source impedance, the shunt capacitors would limit the input bandwidth. theory of operatio the ad6652 has two analog input channels, four digital filter- ing channels, and two digital output channels. the if input signal passes through several stages before it appears at th output port(s) as a well-filtered, decimated digital baseba signal: ? 12-bit a/d conversio ? frequency translation from if to baseband using quadrature mixers and ncos ? second-order resampling decimating cic fir filter (rcic2) ? fifth-order decimating cic fir filter (cic5) ? ram coefficient decimating fir filter (rcf) ? automatic gain control (agc) any stage can be bypassed with the exception of the adc f end. any combination of processing channels can be combined or interleaved after the r a ully utilize the ad6652s capabilities. re employed, the numb ed due to the dual pr flexi (d one output port. four synch frequency hop, and agc functions to be precisely orchestr with other devices. the ncos phase can be set to produce a known offset relative to another channel or device. programming and control of the ad6652 is accomplished using an 8-bit parallel interface. adc architectu
ad6652 rev. 0 | page 25 of 76 e s o ur ce im p e dan c es dr i v in g f o r bes t d y na mic p e r f o r m a n c e , th th e di f f e r e n ti al a n alog i n p u ts s h o u ld be ma t c h e d s u c h tha t co mm o n - m o d e s e t t ling er r o rs a r e symm et r i cal. th e s e er r o rs a r e r e d u ced b y t h e co mm o n -m o d e r e jec t io n o f the ad c. 5pf s 5pf s s = sample h = hold vina+ s h vina ? s h 03198-0-025 f i g u re 38. swit che d - c apaci t o r s h a in put f o r o n e a d c c h ann e l the s h a sh o u ld b e dr i v e n f r o m a s o ur c e t h a t k e eps t h e sig n al p e a k e vol t age. m p u t 5 2 t o e n ti al p u t, a sin g le-en d e d so ur ce can b e dr i v en in t o vin + o r vin ? . n t h is co nf igur a t io n, on e in pu t accep t s t h e sig n al, whi l e t h e o p p o si t e in p u t sh o u ld be set t o m i dscale b y co nn ec tin g i t t o a n a ppropr i a t e re f e re nc e. f o r e x am pl e, a 2 v p - p s i g n a l c a n b e a p plie d t o vin+, w h i l e a 1 v r e fer e n c e is a p plie d t o vin?. the ad6652 t h en accep t s a sig n al va r y in g betw een 2 v a n d 0 v . i n t h e s i ng l e - e nd e d c o n f i g u r a t i o n , d i stor t i on p e r f or m a nc e m i g h t deg r ade sig n if ic a n t l y , co m p a r e d t o t h e dif f er en t i al cas e . h o w e v e r , th e ef f e c t is les s n o t i ce a b le a t lo w e r a n alog in p u t fr e q u e n c i e s . differenti a l input config urations op tim u m p e r f o r m a n c e is achie v ed w h ile dr ivin g th e ad6652 in p u ts in a dif f er en t i a l in pu t conf igura t io n. f o r b a s e b a nd a p p l ic a t ion s t o n y q u is t, t h e ad8138 dif f er en tial dr i v er p r o v ides exce l l en t p e r f o r ma n c e a n d a f l exi b le in t e r f ace t o t h e ad c the o u t p u t co mm on-m o d e v o l t a g e o f the ad8138 is easil y set t o o n e-half o f a v d d , a n d t h e dr i v er c a n be co nf igur e d in a sal l en-k e y f i l t er t o p o log y t o p r o v ide b a n d limi t i n g o f t h e in p u t sig n a l . a t in p u t f r e q uen c ies ab o v e n y q u ist, t h e p e r f o r ma nce o f m o st a m plif iers is n o t ade q u a te t o achie v e t h e t r ue p e r f o r ma n c e o f th e ad6652 ad c s t a g e . e r n r t1 is a c e n t er -t a p p e d , 1: 4 im p e dan c e m e r . th e sig n al c h arac t e r i s t ics m u st s wi t h i n t h e al lo wa b l e ra n g e fo r t h e s e le c t e d r e fer e n c t h e mi nim u m and ma x i m u m c o m m on- o d e i n lev e ls a r e def i n e d as f o l l o w s: vc m min = vref /2 vc m ma x = ( av d d + vref )/2 the m i nim u m co mm o n -m o d e in p u t l e v e l al lo ws th e a d 6 6 acco mm o d a t e g r o u n d -r efer en c e d i n p u ts . al th o u g h o p tim u m pe rf o r m a n c e i s a c h i e v ed wi th a di f f e r this is esp e ci a l ly t r ue in if un ders a m plin g a p pl ica t ion s i n whic h in p u t f r eq uen c ies in t h e ra n g e o f 70 mh z t o 200 mh z a r e b e i n g s a m p le d . f o r t h es e a p pli c a t io n s , dif f er en t i al t r a n s f o r m co u p lin g is t h e reco mm en de d in p u t co nf igura t io n, as sh o w n i f i gur e 39. t r a n s f o r m e ra t i o b r o a d b an d rf t r a n sfo r be co n s i d e r ed wh en se lect i n g a t r a n sf o r m e r . m o s t r f t r ans f or me rs s a tu r a te a t f r e q u e nc i e s b e l o w a f e w m h z, and exces s i v e sig n al p o w e r ca n als o ca us e co r e s a t u ra tio n , which l e a d s to d i stor t i on . ad6652 vina avdd vinb agnd 1v p-p 50 ? 10pf 49.9 ? 50 10pf 1k ? 1k ? 0.1 f ? 03198-0-028 t1 c oup l ed i n p u t for o n e ch anne l of the a d 6 6 5 2 1 / 2 ( av d d + vref ) refb = 1 / 2 ( av d d ? vref ) sp a n = 2 ( reft ? refb ) = 2 vref a s s h o w n b y th e eq ua ti o n s a b o v e , th e r e ft a n d r e fb v o l t a g es a r e symm et r i cal a b o u t t h e midsu p ply v o l t a g e and , b y def i ni t i on, t h e i n p u t sp a n i s t w ice t h e va l u e o f t h e vref vol t a g e . p r o p er o p era t ion o f th e ad6652 r e q u ires tha t vref be n o les s tha n 0.5 v a n d n o g r ea t e r than 1.0 v . the i n t e r n al v o lt a g e r e fer e n c e c a n b e p i n- st ra pp e d t o f i xe d val u es o f 0.5 v o r 1.0 v , o r ad j u s t ed wi thin t h e s a m e ra n g e , as d i scu s sed i n t h e i n t e rn al r e f e r e n c e c o nn ecti o n secti o n . m a xi- m u m snr p e r f o r ma n c e is achi e v e d wi t h t h e r e fer e n c e s e t t o t h e la rgest in p u t sp a n o f 2 v p-p . th e r e la t i v e snr deg r ada t ion is 3 db w h en c h a n g i n g f r o m 2 v p-p m o de t o 1 v p-p m o de . i f o p era t ion usin g a n ext e r n al refer e n c e v o l t a g e is desir e d , i t can be su b s t i t u t e d f o r th e in t e rn al r e f e r e n c e , a s de ta iled in th e e x t e r n al refer e n c e o p era t ion s e c t io n. f i gure 39. d i ffe r e nt ia l a c - adc volta g e reference a s t a b le an d acc u ra t e 0.5 v v o l t a g e r e fer e n c e is b u il t in t o t h e ad6652. th e in p u t s p an o f th e ad c tracks r e fer e n c e v o l t a g e cha n g e s li n e a r ly . an in t e r n al dif f er en t i al r e fer e nce b u f f er cr e a t e s p o s i t i ve a n d ne g a t i ve re fe re nc e volt age s , r e f t and r e f b , r e s p ecti v e l y , tha t d e f i n e t h e s p a n o f th e a d c co r e . t h e o u t p u t co mm o n m o de o f t h e r e fer e n c e b u f f er is s e t t o midsu p ply , a n d t h e ref t an d r e f b vol t a g es and sp a n a r e def i ne d as fol l o w s: reft = i n i
ad6652 rev. 0 | page 26 of 76 h e refer e n c e i n t o fo ur p o ssi b le d , r e f l e c e co nf igura t io n s , reft an d refb dr i v e t h e a/d p u t sp a n . the in p u t ra n g e o f o l t a g e a t t h e r e fer e n c e p i n fo r d r e n o t shown. l t i n g v r e f i n te rna l re fere nce conne c tion 652 det e c t s t h e p o t e n t ial a t t h e i n al l r e fer e n a co m p a r a t o r wi t h in t h e ad6 s e ns e pin and co nf igur e s t st a t es, which a r e summa r i ze d i n t a b l e 11. i f s e ns e is g r o u n d e t h e r e fer e n c e am plif ier s w i t ch is co nne c t e d t o t h e i n t e r n a l r e sisto r divi der ( s e e f i gur e 40) , s e t t i n g vref to a f i xed 1 v re f e re nc e output . c o n n e c t i ng t h e se n s e pi n d i re c t ly to v swi t ch es t h e r e fer e n c e am plif ier o u t p u t t o t h e sens e p i n, co m p letin g t h e lo o p a n d p r o v idin g a f i xed 0.5 v r e fer e n c e output . i f a re s i stor d i v i d e r i s c o n n e c te d, a s s h ow n i n fi g u r e 4 1 , t h e s w i t ch is a g a i n s e t t o t h e s e ns e p i n. this pu ts t h e r e fer e n c e a m plif ier in a no ni n v er t i n g m o de w i t h t h e vr ef p r og ra mma b o u t p ut def i n e d as fol l o w s: vref = 0 . 5 ( 1 + r 2/ r 1) co n v ersio n co r e a n d est a b l ish i t s in t h e ad c alwa ys e q uals t w ic e t h e v ei t h er a n i n t e r n al o r a n ext e r n al r e fer e n c e . the r e fer e n c e am plif ier s w i t ch is lo ca te d n e a r t h e b o t t om lef t . the s e ns e p i n is sh own co n n e c te d to g r o u n d , w h ich s e ts v r e f t o 1 v . deco u p lin g ca p a c i t o r s m u s t be d u p l ica t e d f o r th e c h an nel b a d c c o re, i f i t i s u s e d . t h e c h an ne l b re f am p a n ad c co r e a r e i d en t i cal t o t h os e o f c h a nne l a, b u t a table 11. refer e nce sense o p eration selected mode sense voltage r e s u ( v ) resulting di ffe rential span ( v p-p) external reference avdd e x t e r n a l r e f e r e n c e 2 external reference internal fixed reference vref 0.5 1.0 programmable reference 0.2 v to vref 0 . 5 ( 1 + r 2 / r 1 ) 2 vref (see fi gure 42) internal fixed reference agnd to 0.2 v 1.0 2.0 03198-0-029 vina+ vina? reft_a vref vref to ch b ref amp select core refb_a 0.5v 0.1 f sense logic ch a adc 0.1 f ref amp a 0 .1 f 10 f r int 0.1 f 10 f r int f i gure 40. f i x e d intern al r e f e renc e co nfigur at ion 03198-0-030 vina+ vina ? reft_a vref to ch b ref amp ref amp a ch a adc core refb_a 0.1 f 0.1 f 1 0 vref 0.5v 0.1 f 0.1 f f 10 f r int sense select logic r int r2 r1 where r1 + r2 = 10k ? to 20k ?
ad6652 rev. 0 | page 27 of 76 extern al r e f e r e nc e ope r atio n an ext e r n al r e fer e n c e v o l t a g e can b e us e d t o en ha n c e t h e ga i n a c c u r a c y of t h e a d c or i m prove t h e r m a l d r i f t c h ar a c te r i st i c s . w h en m u l t i p le ad cs t r ack on e a n o t h e r , a sin g l e r e fer e n c e (in t er nal o r ext e r n al) mig h t b e n e ce ss a r y t o r e d u ce ga in- m a t c hin g er r o r s t o a n accep t a b l e lev e l . a hig h -p r e cisio n ext e r n al r e fer e n c e can als o b e s e le c t e d t o p r o v i d e lo w e r ga in and o f fs et t e m p er a t ur e dr if t. w h en t h e s e n s e p i n is tie d t o a v d d as in f i gur e 42, th e in t e r n al r e fer e nce is dis a b l e d , al lo win g t h e us e o f a n ext e r n al re f e re nc e. a n i n te r n a l re f e re nc e bu f f e r l o a d s t h e e x te r n a l r e fer e n c e wi t h an e q ui v a len t 7 k? lo ad . th e i n te r n al b u f f er st i l l g e n e r a t e s t h e p o si t i v e an d nega t i v e f u l l -s c a le r e fer e n c es, reft a n d refb , fo r t h e ad c co r e . th e i n p u t sp an is alwa ys t w ic e t h e val u e o f t h e r e fe r e n c e v o l t a g e; t h er efo r e , t h e exter n al r e fer e n c e m u st b e l i m i te d to a max i m u m of 1 v . i f th e in t e r n al refer e n c e o f the a d 6 6 5 2 s, t h e lo adin g o n vref b y t h e o t h e r con v er t e rs m u st b e o ns i d e r e d . f i g u re 4 4 show s how t h e i n te r n a l re f e re nc e vo lt age is a f fe c t e d b y lo ading. 0 0.2 0.4 0.6 0.8 1.0 1.2 v ref error (%) ?40 ? 30 ? 2 0 ? 10 0 2 0 6 0 10 30 40 50 70 80 90 tempera ture (c) 03198-0-075 v ref = 1v v ref = 0.5v f i g u re 43. t y pic a l v r e f d r if t ?0.25 ?0.20 ?0.15 i s u s ed t o dr i v e m u l t i p le i c c 03198-0-031 vina+ vina? vref 0.5v to 1.0v external reference in vref sense +3.0v to ch b ref amp select logic ref amp a ch a adc core reft_a refb_a 0.5v 0.1 f 0.1 f 0.1 f 0.1 f 10 f 10 f r int r int f i gure 42. ex ter n al refer e n c e o p er ation with c o nn ec tions sho w n for channe l a o n ly ?0.10 rror (%) ?0.05 0.05 e 1.0 1.5 0 0.5 2.0 2.5 3.0 load (ma) 03198-0-076 0 1v error 0.5v error f i g u re 44. v r e f ac cur a c y v s . l oad shared reference mode the sha r e d r e fer e n c e m o de al lo ws t h e us er t o c o nn e c t t h e r e fer e n c es f r o m t h e d u al ad cs t o g e t h er fo r su p e r i o r ga in a n d o f fs et ma t c hi n g p e r f o r ma n c e . i f t h e ad c s a r e t o f u n c t i on indep e n d en t l y , t h e r e fer e nce de c o u p lin g sh o u ld b e t r e a t e d indep e n d en t l y and can p r o v ide su p e r i o r is ola t i o n b e twe e n t h e d u a l a d c ch an nel s . t o e n abl e s h are d re fe re nc e mo d e , t h e s h rd ref p i n m u st b e t i e d hig h an d t h e dif f er en t i al r e fer e n c e s m u st b e e x te r n a l ly shor te d to ge t h e r , t h a t i s , r e f t a m u st b e shor te d e x te r n a l ly to r e f t b and r e f b a m u st b e s h or te d e x te r n a l ly to r e f b b .
ad6652 rev. 0 | page 28 of 76 ve n with a nominal 50% duty cycle. duty cycle b w affec e crea sam low the quire and lock to the new rate. gh the c inpu f input ) due only to aperture jitter (t a ) can be in the equation, the rms aperture jitter, t , represents the root- t, signal with digital noise. low jitter, nal last s e power dissip d by the ad6652 front-end ad is propor- nal to its samp g rate. norma dc operation uires that th pdwn pin e set to logic lo he adc can placed in ower-down m e by setting bo pdwn pins t gic high. w power dissi ion in power-d n mode is ach ed by tting down th eference buffers and biasing ne rks of th adc chann . both power- pins must b riven ether either h or low for pro r adc operat . r maximum p er savings, the lk and analo put(s) ould remain st while in stan mode, result in a ical power co ption of 1 m for the adc. he clock uts remain ac while in stan mode, typical power nsumption for e adc is 12 mw adc wake-up time upling capacitors on reft and refb are discharged de, and then must be recharged when the upling capacitors on reft and y discharge the e buffer decoupling capacitors, and 5 ms to restore full n. clock input considerations typical high speed adcs use both clock edges to generate a modulating the clock crystal-controlled osci variety of internal timing signals, and as a result can be sensiti to aclk clock duty cycle. commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic perform- ance characteristics. the ad6652 contains a clock duty cycle stabilizer that re-times the nonsampling edge, providing a internal clock signal sta ilizing is engaged by setting dutyen to logic high. this allo s a wide range of aclk clock input duty cycles without ting the performance of the ad6652 adc stage. th duty cycle stabilizer uses a delay-locked loop (dll) to te the nonsampling edge. as a result, any changes to the pling frequency require approximately 2 ms to 3 ms to al dll to ac hi speed, high resolution adcs are sensitive to the quality of lock input. the degradation in snr at a given full-scale t frequency ( calculated with the following equation: snr degradation = 20 log10 [1/2 p f input t a ] a sum square of all jitter sources, which include the clock inpu analog input signal, and adc aperture jitter specification. undersampling applications are particularly sensitive to jitter. to minimize clock jitter, treat the aclk clock input as an analog signal. power supplies for clock drivers should be separated from the adc output driver supplies to avoid llators make the best clock sources. if the aclk clock is generated from another type of source (by gating, dividing, or other methods), re-time it by the origi clock at the tep. adc power-down mode th ate c tio lin l a req bo s b w. t be a p od th o lo lo pat ow iev shu e r two bo els down e d tog igh pe ion fo ow ac g in sh atic dby ing typ nsum w if t inp tive dby co th . the deco when entering standby mo returning to normal operation. as a result, the wake-up time is related to the time spent in standby mode. shorter standby cycles result in proportionally shorter wake-up times. with recommended 0.1 f and 10 f deco refb, it takes approximately 1 s to full referenc operatio
ad6652 rev. 0 | page 29 of 76 cture ove data input matrix t n - more into in-phase (i) and quadrature (q) components. this stage translates the input signal from a digital intermediate frequency (if) to digital baseband. phase and amplitude dither can be enabled on-chip to improve spurious performance of the nco. a phase-offset word is available to create a known phase relationship between multiple ad6652s or between channels. second-order rcic filter following frequency translation is a resampling, fixed coefficient, high s g cascade integrator comb (rcic2) filter, which reduces the sample rate etween the master clock and the output data rate. this stage can be bypassed by setting the decimation/interpolation ratio to 1. fifth-order cic filter the next stage is a fifth-order cascaded integrator comb (cic5) filter, whose response is defined by the decimation rate. the purpose of these filters is to reduce the data rate to the final filter stage and to provide antialias filtering. the reduced data rate allows the ram coefficient filter (rcf) stage to calculate more taps per output. a r beyond the 160 tap maximum. s a t igersharc. a multiplexer for each port f e l figure 45 illustrates the basic function of the ad6652, that is, to select and filter a single carrier from a wide input spectrum and to down-convert it to baseband data. figure 46 shows examples of the combined filter response of the rcic2, cic5, and rcf for narrowband and wideband carriers. digital downconverter archite rview based on the ratio between the decimation and interpolation registers. the resampler allows for noninteger relationships ram coefficient filter the ram coefficient filter (rcf) stage is a sum-of-products fir filter with programmable 20-bit coefficients, and decima- tion rates programmable from 1 to 256 (1 to 32 in practice). each ram coefficient fir filter (rcf in figure 1) can handle maximum of 160 taps. two or more rcf stages can be com- bined using flexible channel configuration to increase the processing powe the digital downconverter (ddc) section features dual high speed 12-bit input ports that are capable of crossbar multiplex- ing of data to the four processing channels that follow the inpu matrix. in addition, a third input option to the matrix is available to facilitate bist (built-in self-test). this option is a pseudorandom noise (pn) sequence. the dual input ports permit diversity reception of a carrier, or they can be treated as unrelated and independent inputs. either input port or the p sequence can be routed to any or all four tuner channels. this flexibility allows up to four signals to be processed simultane ously. refer to the ddc input matrix section for a complete description. numerically controlled oscillator frequency translation is accomplished with a 32-bit complex numerically controlled oscillator (nco). each of the four processing channels contains a separate nco. real data entering this stage is separated peed, second-order, resamplin b the rcf outputs of each channel can be directly routed to one or both output ports or to an agc stage, where selected ddc channels can be interleaved and interpolated in a half-band filter, if desired. interpolating half-band filters and agc processed rcf data can also be routed to two half-band interpolation stages, where up to four channels can be combined (interleaved), interpolated by a factor of two, and automatic gain control (agc) applied. each agc stage ha dynamic range of 96.3 db. these stages can be bypassed independently of each other. the outputs from the two agc stages are routed to both output port multiplexers. each outpu has a link port to permit seamless data interface with dsp devices such as the t selects one of the six data sources to appear at the device parallel or link output pins. the overall filter response for the ad6652 is the composite o all decimating and interpolating stages. each successive filter stage is capable of narrower transition bandwidths, but requires a greater number of clk cycles to calculate the output. mor decimation in the first filter stage helps to minimize overal power consumption.
ad6652 rev. 0 | page 30 of 76 f r e q u e n c y t r a n s l a t i o n ( f o r e x a m p l e , s i n g l e 1 m h z c h a n n e l t u n e d t o b a s e b a n d ) a f t e r f r e q u e n c y t r a n s l a t i o n nco tunes signal to baseband dc signal of interest image signal of interest w i d e b a n d i n p u t s p e c t r u m w i d e b a n d i n p u t s p e c t r u m ( f o r e x a m p l e , 3 0 m h z f r o m h i g h s p e e d a d c ) 03198-0-032 f /2 f /4 s s s f /8 ?f s /8 ?f s /4 ? f s /2 ?3 f s /16 ?3 f s /8 ? 5 f s /16 ?f s / 1 3 f /8 5 f /16 (? f sample /2 to + f sample /2) 6 dc f s /2 ?f s /8 ?f s /4 s s s s 3 f /16 f /16 f s /4 f s /8 ? f s /2 3 f s /8 5 f s /16 ?3 f s /16 ?3 f s /8 ? 5 f s /16 ?f s /16 f i gur e 4 5 . ad66 52 f r e q ue nc y t r ansl a t i o n 3 f s /16 f s /16 o f w i de ba nd input sp e c tr um ?1.53 10 4 ?1.03 10 4 1.03 10 4 1 . khz ? 120 ?5000 0 5000 20 5 3 1 0 4 dbc ?40 ?60 ?80 ? 100 0 ?20 ? 1000 khz ? 800 ?600 ?400 ? 200 0 200 400 600 800 1000 03198-0-033 ns. na rro we r f ilt er ( r ig ht ) d e s i g n ed f o r e d ge a p pli c at ion 1 . 6 k s ps d d c o u t p ut rate) dbc ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 if ic at i o te and 5 4 f i g u re 46. f i lte r r e s p ons e ( l ef t ) m eet s u m t s ( w id eba n d) spec (65 m s ps a d c co nvers i on ra
ad6652 rev. 0 | page 31 of 76 memory map addre n ory l register addresses that begin with 0x indicate that that follows is in hexadecimal notation. dress modate register data that is 20 bits wide; number(s), in decimal format, of the function that is being described. eight, 3-bit external memory map addresses are shown in decimal format in table 22. each of these addresses can accommodate 8 bits of register data. decimal addressing example: 7:4 indicates that this is an external memory address (no 0x prefix) and that the binary address is 111, because only 3 external address bits are assigned. also, only bit 4 of the 8-bit data field is described or referred to. hex addressing example: 0x0a:7C0 indicates that the binary address is 00001010 and that bits 7 through 0 are involved with the function being described. because this address begins with 0x, the user knows that it is not an external memory address, and can be either an individual channel address register or an output port control register, depending upon how it was routed using the external memory address registers. the largest 8-bit address that is used in the hexadecimal address scheme is a9 or 169 decimal. this might not seem to be enough memory addressing capacity, but, because addresses are re-used with the external memory mapping scheme, there is no shortage of address capability. ddc input matrix the digital downconverter stages feature dual high speed crossbar-switched input ports that allow the most flexibility in routing the two adc data streams to the four receive process- ing channels. crossbar switching means that any of the four processing channels can receive data from either port a or port b for a total of 16 possible combinations, as shown in table 12. input port routing is selected in each ncos control register at 0x88:6. control register and ss notatio the following sections make frequent references to program- mable registers and the memory mapping structure of the ad6652. a good overview of the control registers and memory mapping structure is found beginning in the external mem map section. the following conventions are used in this addressing scheme: ? contro the address ? cimal addresses are 8 bits wide, and each ad all hexade can accom however, many of the available 20 bits per address are unused. ? a colon following an address indicates the specific bit ? table 12. crossbar-switched routing of the two 12-bit adc data streams (a and b) using the ddc input matrix channel 3 channel 2 channel 1 channel 0 a a a a a a a b a a b a a a b b a b a a a b a b a b b a a b b b b a a a b a a b b a b a b a b b b b a a b b a b b b b a b b b b ddc data latency the overall signal path latency from ddc input to output can be expressed in high speed clock cycles. use the following equation to calculate the latency: t latency = m rcic2 (m cics + 7) + n taps + 26 where: m rcic2 and m cic5 are decimation values for the rcic2 and cic5 filters, respectively. n taps is the number rcf taps chosen. gain switching the ad6652 includes circuitry that is useful in applications in which large dynamic range input signals exist. this circuitry allows digital thresholds to be set such that an upper and a lower threshold can be programmed. one use of this circuitry is to detect when an adc is about to reach full scale with a particular input condition. the results provide a flag can quickly insert an attenuator to prevent adc overdrive. if 18 db (or any arbitrary value) of attenuation (or gain) is switched in, then the signal dynamic range of the system is increased by 18 db. the process begins when the input signal reaches the upper programmed threshold. in a typical application, this might be set 1 db (user definable) below full scale. when this input condition is met, the appropriate li (lia, lia , lib or lib ) signal associated with either the a or b input port is made active. this can be used to switch the gain or attenuation of the external circuit. the li line stays active until
ad6652 rev. 0 | page 32 of 76 m m e d w e r in p u t sig n al g o e s a b o v e t h e u p p e r t h r e sh old , t h e a p p r o p r i a t e li sig n al becom e s a i v e . on ce t h e sig n al fal l s be lo w t h e lo w e r t h r e sh old , t h e c o un ter b e g i ns c o un t i ng. i f t h e i n p u t condi t ion g o es a b o v e t h e l o w e r t h r e sh old , t h e co u n t e r is r e s e t an d st a r ts th e in p u t co n d i t i o n falls be lo w th e lo w e r p r o g r a th r e s h o l d . t o p r o v ide h y ster esis, a d w e l l t i m e r e g i st er (s e e t a b l e 28) is a v a i la b l e t o h o l d o f f swi t c h in g o f th e co n t r o l lin e f o r a p r e d et er mi n e d n u m b er o f clo c ks. on c e t h e i n pu t co ndi t io n is b e lo w t h e lo w e r t h r e sh old , t h e pr og ra mma b l e co un t e r b e g i ns co un t i n g hig h sp eed c l o c ks. a s lo n g as t h e in p u t sig n al s t a y s b e lo w t h e lo w e r t h r e sh old fo r t h e n u m b er o f hig h sp e e d clo c k c y cles p r og ra mm e d , t h e a t t e n u a t o r is r e m o v e d o n t h e t e r m inal co un t. h o w e v e r , if t h e i n p u t condi t ion g o es ab o v e t h e lo th r e s h o l d wi th t h e co un t e r r u n n i n g , i t i s r e se t a n d m u s t fall b e lo w t h e lo w e r t h r e sh old a g a i n t o ini t i a t e t h e pr o c ess. this p r ev e n t s u n n e ce s s a r y sw i t c h i n g bet w een s t a t e s . thr e sh old s e t t in gs fo r li a r e il l u s t ra t e d in f i gur e 47. w h e n t h e c t a g a i n, as sh o w n in t h e f i gur e . on ce t h e co un t e r has t e r m ina t e d t o 0, t h e li li n e g o es inac t i v e . high mantis s a dwell time low upper threshold lower threshold counter restarts time 03198-0-034 f i gur e 4 7 . thr e shold setti ngs for li t h e li lin e ca n be use d f o r a var i ety o f f u n c tio n s. i t ca n be use d to s e t t h e c o n t r o l s of an a t t e n u a t or , dv g a , or i n t e g r a t e d a n d used wi t h a n analog v g a. t o sim p lif y th e use o f this f e a t ur e , the c l udes tw o s e p a ra t e ga in s e t t in gs, o n e w h en t h is lin e e (rci c2_q uiet[4:0 ] s t o r ed in b i ts 9:5 o f 0x92 a c ti v e (rci c2_lo u d[4:0] s t o r ed be e and e x te r n a l a tte n u a t or g a i n ( i f u s e d ) . i f no e x te r n a l a t t e n u a t o r i s u s e d , b o th th e r c i c 2 _ q u i e t a n d r c i c 2 _ l o u d in o m i nim i ze l o o p de l a ys. an y o f th e f o ur s t a in s a co r r e c t s c a l e val u e th r o u g h o u t th e p r oce s s , m a ki n g i t t o tall y in d e p e n d en t . th e ad6652 in c l udes a p r og ra m m a b l e p i p e lin e dela y tha t can be used t o co m p ensa t e f o r the in h e r e n t 7-c l o c k p i p e lin e de l a y a s soci a t e d wi th th e f r o n t- en d ad c . t h i s f e a t u r e p r o m o t e s sm o o t h er s w i t chin g am o n g ga in s e t t in gs. ad6652 in is inac ti v r e g i s t er) a n d t h e o t h e r w h e n e g in b i ts 4:0 o f 0x92 r i s t er). this al lo ws th e dig i tal ga in t o ad j u s t e d t o t h e ext e r n al c h a n g e s. i n co n j un c t io n wi th t h e g a in s e t t in g, a va r i a b le h o ld-o f f is i n clu d e d to c o m p e n s a te for t h e p i p e li n e de l a y o f t h e ad c and t h e s w i t chin g t i m e o f t h e ga i n co n t r o l e l e m en t. t o g e t h er , t h es e tw o fe a t ur es p r o v ide s e a m l e s s ga in s w i t c h in g. rcic2_ lou d [4:0] and rcic2_ quiet[4:0] th e s e 5- b i t r e g i st ers co n t a i n s c ale val u es t o co m p e n s a t e fo r t h r c ic 2 g a i n r e g i st ers co n t a i n t h e s a m e va l u e . th e s e 5- b i t s c ale val u es a r e s t o r ed in t h e rci c 2 scale r e gi st er (0x92) a n d th e scali n g i s a p plie d b e fo r e t h e da t a en ters t h e rcic2 r e s a m p lin g f i l t er . b o th d d c in p u t p o r t s o f th e ad6652 ha v e in dep e n d en t g a c o n t ro l c i rc u i t s , a l l o w i ng e a ch re sp e c t i v e l i pi n t o b e pro - g r a m m e d t o dif f er en t s e t p o in t s . n o t e t h a t t h e i n p u t ga i n co n t r o l cir c ui ts a r e wideb a n d and a r e i m pleme n t e d p r io r t o a n y f i l t er in g e l em en ts t d d c p r o c essing cha n n e ls can b e s e t t o m o ni t o r ei t h er o f t h e dd c i n put p o r t s . the chi p als o p r o v ides a p p r o p r i a t e s c ali n g o f t h e in ter n al da t a , b a s e d o n t h e a t t e nu at i o n a s s o c i at e d w i t h t h e l i s i g n a l . in t h i ma nn er , da t a t o t h e ds p main
ad6652 rev. 0 | page 33 of 76 t r o l l e d o s c i l l a tor of t w o m u lt i p l i e r s , i an d q , an d a 3 2 - b i t c o m p l e x n u me r i c a l l y co n t r l l ed os cil l a t o r (n c o ). e a c h c h a n ne l o f the ad6652 has p e n d e n t n c o . th e n c o s e r v es as a q u adra t u r e lo ca l r c a p a ble o f p r o d ucin g a n nco f r e q ue n c y be tw e e n 8 6 i s sig n e d in teger . u s e t h e fol l o w in g e n c o f r eq u e n c y : nume r icall y c o n frequenc y tr ansl a t i o n t o base band t h i s pro c e s s i ng st a g e c o m p r i s e s a d i g i t a l tu ne r c o ns i s t i ng o a n i n de os cil l a t o ?clk /2 an d +c lk /2 wi t h a r e so l u tio n o f clk/2 32 in t h e com p lex m o de . th e w o rst-cas e sp ur io us sig n al f r o m t h e n c o is b e t t er tha n ? 1 0 0 d b c fo r al l o u t p u t f r e q uen c ies. the nco f r eq uen c y p r og ra m m e d in reg i s t ers 0x85 a n d 0 x in t e r p r e t e d as a 32-b i t u n eq ua ti o n t o c a l c ul a t e t h ? ? ? ? ? ? = clk f freq nco 32 2 _ w h er e: nc o _ f r e q is a decimal n u m b er eq ual t o t h e 3 2 -b i t b i na r y ed a t 0 x 85 a n d 0x86. clk is t h e ad6 652 d d c mast er c l o c k ra t e (in h z ). a shado w r e g i st er gen e ra l l y p r e c e d es an ac t i ve r e g i ster . i t h o ld s th e n e xt n u m b er t o be used b y t h e a c t i v e e gi s t er wh en ev e r th a t f u n c tion s h o ld-o f f co un t e r ca us es th e ac t i v e r e g i s t er t o b e - o r t . ly f rom s er l ly c y ) a r ts co un tin g do wn a t t h e d d c clk r a t e and , when i t r e ach e s o n e , t h e ne w f r e q uen c y val u e i n t h e s h ado w r e g i s t er is wr i t t e n to t h e ac t i v e nc o f r e q uen c y r e g i s t er . e t t in g c y u e s. e e e p h a et r ( 0 d d g ra le o o e phas m u f t o . this 16 -b t e r r - et ed as a 16-b i t e d r . a 0x0000 in this r e g r r es po n o , a n f f r es t o e t 2 r a t h s t e r m n c b e nc h r o p e o w i s t a n n e dif c e s. o c o i s h e c o n g i s t e 8 8 i g u ur e s n c i c h n t n h a n th a t u n o l l o s e c t a ss t o b y p a s s t h e nco o f th e ad6 652, s e t b i t 0 o f 0x88 hig h . w h en t h e n c o is b y p a ss e d , do w n -con e rsio n is n o t p e r f o r m e d , an d lex - d i g i tiz e d s i gn al h a s alr e a d y been con v er t e d t o bas e band in p r io r a n alog s t a g es o r b y o t h e r f t h e nc o . t o ena b l e phas e di t h er , s e t e n o is e f l o o r a n d s p ur io us f r e e d y na mic ran g e is in cr eas e d a t t h e exp e n s e o f s l ig h t decr eas e s in s t e m urs a r e o r , t h en phas e t t h er am p l i t ude di t h er ca n als o b e us ed t o im p r o v e s p ur io us p e r f o r ma n c e o f t h e n c o . t o ena b le a m pl i t ude di t h er , s e t bi t 2 o f 0x88, whic h c a us es a m p l i t ude q u a n tiza tion er r o r s t o be ra n d omi z e d wi t h in t h e an gu la r - t o -c a r t e sian con v ersio n s t a g e of t h e n c o . t h i s opt i on re d u c e s spu r s a t t h e e x p e ns e of a slig h t ly ra is e d no is e f l o o r a n d slig h t ly r e d u ce d snr . a m pli t ude di t h er an d phas e di t h er c a n b e us e d t o g e t h er , s e p a ra t e l y , o r n o t at a l l . n u m b er t o be p r og ra m m f is t h e desir e d n c o o u t p ut f r e q uen c y in hz. nc o shad ow register r u p da te d w i t h t h e ne w v a l u e . a c t i v e r e g i s t ers a r e als o u p da t e d wi t h t h e con t en ts o f a s h ado w reg i s t er an y tim e th e c h ann e l i s brou g h t out of sl e e p mo d e . t h e n c o sh a d ow re g i ste r i s up d a t e d d u r i ng n o r m a l pro g r a m m i ng of t h e re g i ste r s t h rou g h t h e m i c rop or t or s e r i a l i n put p t h e a c t i v e f r e q u e nc y re g i ste r c a n re c e iv e up d a te d a t a on t h e nc o sh a d ow re g i ste r . whe n s o f t w a re re a d s b a ck a n n c o f r eq ue n c y , i t i s r e a d i n g ba c k t h e a c ti v e f r eq ue n c y r e gi s t e r a n d not t h e sh a d ow re g i ste r . nc o frequ e nc y hol d - o ff regist w h en t h e n c o f r e q uen c y r e g i s t ers a r e wr i t t e n, da t a is ac t u a p a ss e d to a sha d ow re g i ste r . d a t a c a n b e move d to t h e ac t i ve re g i ste r by one of t w o me t h o d s : w h e n t h e ch a n ne l c o me s out o f sl e e p m o d e or w h e n a s y nc h o p o c c u r s . a s a re su lt of e i t h e r ev en t, a co u n t-do wn co un t e r is lo aded wi t h a n n c o f r eq uen h o ld-o f f val u e . the 16-b i t un sig n e d in t e g e r coun t e r ( 0 x 8 4 the nco can b e s e t u p t o u p da t e i t s f r eq uen c y imm e dia t e l y up on re c e ipt of a hop _ sy n c o r st a r t _ sy n c , w i t h no h o ld-o f f co un t, b y s e t t in g t h e hold-o f f co un t v a l u e t o 1. s th e h o ld-o f f coun t t o zer o p r even ts an y f r eq uen p da t p h a s o f fs t t h s e o f fs e g i s t e r x 8 7 ) a s a p r o mma b f fs et t t h e acc u l a t o r o h e n c i t r e g i s i s i n t e p r u n sig n in t e g e i s t er c o n d s t o o f f s e t d a 0 x f f c o r po n d s a n o f f s o f d i a n s. i s r e g i a l lo w s u l t i p l e o s t o s y n i z e d to r o d u c u t p u t s t h c o n t an d k o w n phas f er en n c o n t r l r e g t e r u s e t n c o t r o l r e t er lo c a d a t 0 x t o c o n f r e t h e f e a t o f th e o , w h a r e c o r o l l e d o a p e r c n e l b a sis. e s e fe r es a r e des c r i b e d i t h e f w in g i o n s . b y p v th e ad6652 c h anne l f u n c tio n s s i m p l y as a r e al f i l t er o n com p d a t a . this fe a t ur e is us ef u l fo r bas e b a n d s a m p li n g a p pli c a t io n s , wh e r e th e a in p u t i s co nn ect e d t o th e i s i gn al p a th wi th in th e f i l t er a n d t h e b i n p u t is conn e c te d t o t h e q sig n al p a t h . byp a s s i n g th e n c o m i gh t be d e s i r e d , if th e dig i t a l p r ep r o ces s in g. phase dither the ad6652 p r o v ides a p h as e di t h er o p tion f o r im p r o v in g t h e s p ur io us p e r f o r ma nce o bi t 1 o f reg i st er 0x88, w h ich c a us es dis c r e t e s p urs d u e t o phas e tr un ca t i o n in t h e n c o t o b e ra n d omize d . th e en erg y f r o m t h es e s p urs is s p r e ad in t o t h t h e snr . th e ch o i ce o f w h et h e r t o us e phas e di t h er i n a s y dep e n d s u l t i ma te l y o n t h e sys t e m g o als. i f lo w e r s p desir e d a t t h e exp e n s e o f a s l ig h t ly ra is e d n o i s e f l o di t h er sh o u ld b e em plo y e d . i f t h e lo w e s t n o is e f l o o r is desir e d a n d hig h er sp urs ca n be t o lera t e d o r f i l t er ed b y s u bs e q u e n s t a g es, t h en phas e di t h er is n o t n e e d e d . a m p l i t u d e d i s t
ad6652 rev. 0 | page 34 of 76 umulator is cleared et is e beginning phase for the new frequ ncy. reserved bits put en input port b is connected to the selected filter channel. if this bit is cleared, then input port a is connected to the lected filter channel. sync pin select bits 7 and 8 of the nco control register determine which t. ync pins: synca, syncb, syncc, and be enabled in nal o a h b u el ecifi al in. ble r g el ss r ts to se a n se nc dre x8 ad bit 0x88:7 ted c pin clear phase accumulator on hop when bit 3 is logic high, the nco phase acc (set to all zeros) at the beginning of the next frequency change. this ensures a consistent phase of the nco on each hop by defeating the phase continuous feature. the nco phase offs unaffected by this setting. if phase continuous hopping is desired, this bit should be cleared so that the last phase in the nco phase register becomes th e bits 4 and 5 are reserved and should be written to logic 0. input select bit 6 of the nco control register at address 0x88 controls in port selection. if this bit is set high, th se external sync pin (if any) is assigned to the channel of interes the ad6652 has four s syncd. any sync pin can be assigned to any or all four receiver channels of the ad6652; however, a channel can have only one o sync pin assigned to it. the sync pin(s) must als the pin_sync control register at address 4 of the exter mem ry map. t ble 13 s ows the it values sed to s ect a sp c extern sync p ta 13. prog ammin chann addre egister ( car) bi choo sync pi for a lected o ad ss/bit 0 8:8 dress/ selec syn 0 0 a sync 0 1 b sync 1 0 c sync 1 1 syncd
ad6652 rev. 0 | page 35 of 76 r d c ta - lo w e d in t h e rcic2. th e r e s a m p lin g fac t o r fo r t h e rci c 2 (l) is a 9-b i t in teg e r . w h en c o m b in e d wi t h t h e decima tion fac t o r m, a 12-b i t n u m b er , t h e t o t a l ra t e -cha n g e c a n b e an y f r ac t i o n in t h e fo r m o f second-order rcic fil t e the rci c 2 f i l t er is a s e cond-o r d er r e s a m p lin g c a s c ade d in teg r a t o r com b f i l t er . th e r e s a m p ler is im ple m e n t e d usin g a uniq ue t e chnique , w h ich do es n o t r e q u ir e t h e us e o f a hig h - sp e e d clo c k, t h u s sim p lif y in g t h e desig n and s a vin g p o w e r . th e r e s a m p ler al lo ws f o r n o nin t eg er r e la tion s h i p s b e tw een t h e d c l k a n d t h e o u t p u t da t a ra t e . th i s allo w s ea s i e r i m p l em en t i o n o f sys t em s t h a t a r e e i t h er m u l t i m o d e o r r e q u ir e a mas t er c l oc k th a t i s n o t a m u l t i p le o f th e da t a ra t e t o b e used . i n t e r p ol a t ion u p t o 512 a n d de cima tion u p t o 4096 is al 1 2 2 = rcic r m l r rcic t h e o n l y co t h an or i c 2 d e ci m a t e s b y 1 o r a sec o n d - o r d e r c a sc ad e d c t e r i s t ics a r e det e r m i n e d o n ly ). r t g n s tra i n t i s tha t t h e ra ti o l/m m u st b e l e ss e q ua l t o on e . th is im plies t h a t t h e r c more. r e sa m p li n g i s im p l em e n t e d b y a p pa r e n t l y in cr ea si n g t h e in p u t s a m p le ra t e b y th e fac t o r l, usin g zer o s t uf f i n g fo r th e n e w da ta sa m p l e s . f o ll o w i n g th e r e sa m p le r i s in teg r a t o r com b f i l t er . f i l t e r c h a r a b y th e f r a c ti o n a l ra t e - c ha n g e (l/ m the f i l t er can p r o c es s sig n als a t t h e f u l l ra te o f t h e i n p u t p o (65 mh z). th e o u t p u t ra te o f this s t a g e is g i v e n b y th e f o l l o w i n eq ua ti o n : 2 2 2 rcic samp rcic samp m f l f = w h er e: l rc i c 2 a nd m rc ic 2 are u n s i g n e d i n t e ge rs . l rc i c 2 , th e in t e r p ola t ion ra te , can be f r o m 1 t o 51 2. m rc i c 2 , th e decima tion, can b e betw een 1 an d 4096. the s t a g e c a n b e b y p a s s e d f r eq uen c y r e s p o n s e o f th e b y s e t t i n g t h e de ci ma t i on t o 1/1. th e r c i c 2 f i l t er is g i v e n b y th e f o l l o w in g eq ua ti o n s : 2 2 1 ? ? ? ? ? m z rcic 1 2 2 1 2 1 ) ( 2 ? ? ? ? ? ? ? = ? z l l z rcic rcic s rcic ? ? ? ? h 2 2 2 2 sin sin 2 1 ) ( 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = samp samp rcic rcic rcic s f f f l f m l f h rcic u s e t h es e e q ua t i o n s alo n g wi t h t h e fol lo win g f i l t er t r a n sfer e q u a t i o n s t o cal c u l a t e t h e gain and p a ss- b an d dr o o p o f t h e rci c 2. e x ces s i v e p a s s -b an d dr o o p c a n be co m p en s a t e d f o r in c rci c 2 to t h e le ast a t t e n u a t ion wi t h o u t cr e a t i n g an t m u s t be p r og ra m m e d a t 0x92 e v a u ld t 0x92[4:0] t da t e t rdw a re f e a t u r e. a ss-b a n d d o f t h e r c i c 2 sho u l t h e rcf st a g e b y p e akin g t h e p a ss-b an d b y t h e in v e rs e o f t h e ro l l - o f f . rcic2 sc ale f a c t or the s c ale f a c t o r , s rci c 2 , is a p r o g rammabl e u n s i g n e d 5 - b i t betw een 0 an d 31, whic h ser v es as a n a t t e n u a t o r tha t can r e d u ce t h e ga i n o f t h e rci c 2 i n 6 db i n cr em e n ts. f o r t h e b e st d y nami ra n g e , set s o v erf l o w co n d i t io n. t h is ca n be s a f e l y acco m p lis h e d usin g t h e fol lo win g e q u a t i o n , w h er e input _ l e v e l is t h e la rgest f r ac t i o n o f f u l l s c ale p o ssible a t t h e i n p u t to t h e ad6652 ( n o r mal l y 1). the s rci c 2 s c ale fac t or is alwa ys us e d whet her o r n o t t h e rcic2 is by p a s s e d . the s rci c 2 val u e m u s t be les s than 32 o r th e in ter p o l a t io n an d de c i m a t i on r a te s m u st b e a d j u st e d to v a l i d a te t h i s e q u a t i on. the ce il f u nc t i o n d e note s t h e ne x t w h o l e i n t e ge r , an d t h e fl o o r f u n c t i on de n o t e s t h e c u r r en t w h ole i n t e g e r . f o r exa m ple , t h e ce il (4.2) is 5 w h i l e th e fl o o r (4.2) is 4. w h en s rci c 2 has b e en det e r m in e d f o r al l c h a n n e ls, i a d d r [9:5] o f e a ch cha nne l o be p r og ra m m e d a ess r e g i st er . the s a m o acco m m o l u e sh o als a r e d u ndan h a the ga i n an d p r o o p d b e ca lc u - la ted b y t h e p r e v io us eq ua tio n s, as w e l l as t h e r c i c 2 f i l t er tra n s f e r eq u a ti o n s . ex ce s s i v e pa s s - b a n d d r oo p ca n be co m p en - s a t e d fo r in t h e r c f st a g e b y p e akin g t h e p a ss- b a nd b y t h e in v e rs e o f t h e rol l -o f f . ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 2 log 2 2 2 2 2 2 2 2 2 rcic rcic rcic rcic rcic rcic rcic rcic l m floor l m l m floor m ceil s ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1
ad6652 rev. 0 | page 36 of 76 e r s c alin g fac t o r has b e en det e r m i n e d , t h e o u t p u t rcic2 output level af t e r t h e p r o p le v e l f r o m t h e r c i c 2 s t a g e ca n b e de t e r m i n e d usin g t h e f o l l ow i n g e q u a t i on : () level input l m ol rcic rcic _ 2 2 = rcic s rcic 2 2 2 2 l e ( o r 1) f r o m th e ad c t o t h e i l l u s t ra t e s t h e am o u n t o t h in p e r c en t a g e o f i c 2 s t a g h e d a t a in t h i s ta b l e ca n be l l o wa b l e s a m r a te u p t o 65 mh z. th e s e d as a to ol to de c to di st r i b u te t h e e s a m p le ra t e t h a t is r e p en t e d b y t h e p a s s b a n d , as fol l o w s: wher e: input _ le v e l is n o r m al l y f u l l s c a rci c 2 s t a g e . ol rc i c 2 is t h e o u t p u t l e v e l f r o m t h e rcic2 s t a g e exp r es s e d as a f r a c t i on of t h e in pu t _ le v e l . ol rc i c 2 is us ed la t e r in the ci c5 s t a g e-leve l calc u l a t io ns. rcic2 re jec t io n t a b l e 1 4 f b a n d wid th e da ta ra t e i n t o th e rc e . t scaled t o an y o t h e r a p l e t a bl e c a n b e u i de how d e ci ma ti o n betw ee n rc i c 2, c i c 5 , a n d t h e r c f . ex a m p l e ca l c ul a t i o n s : go al : i m p l em en t a f i l t er wi th an in p u t s a m p le ra t e o f 10 mh z , r e q u ir in g 100 db o f alias r e jec t io n f o r a 7 kh z p a s s ban d . so l u t i o n : f i rs t det e r m i n e t h e p e r c en t a ge o f t h r es 07 . 0 mhz 10 khz 7 100 = = fraction bw then f i nd the ?100 db col u mn o n the r i g h t o f t h e tab l e and lo o k do wn this co l u m n f o r a va l u e gr ea t e r tha n o r eq ual t o t h e p a s s -band p e r c en ta ge o f th e c l o c k ra te . th en lo o k acr o s s t o th e ext r em e lef t column and f i nd t h e co r r es p o n d i n g ra t e cha n g e fac t o r (m rci c 2 /l rc i c 2 ). r e f e rri n g t o th e ta b l e , n o tice th a t f o r a m rci c 2 /l rci c 2 o f 4, th e f r eq uen c y ha vin g ?100 db o f alias r e jec t io n is 0.07 1%, which is s l ig h t l y g r ea t e r tha n t h e 0.07 % calc u l a t e d . ther efo r e , fo r t h is exa m ple , t h e maxi m u m b o u n d o n rci c 2 ra te c h a n g e is 4. a hig h er c h os en m rc i c 2 /l rci c 2 me ans l e ss alias r e j e c t io n t h a n t h e 100 db r e q u ir ed . an m rci c 2 /l rci c 2 o f les s tha n 4 w o u l d s t il l yie l d t h e r e q u ir ed r e j e c t io n; h o w e ver , p o w e r co n s um p t ion can b e minim i ze d b y d e ci ma ti n g a s m u c h a s pos s i b le i n th i s rc i c 2 s t a g e . d e ci ma tio n i n rc i c 2 lo w e r s th e da ta ra t e , a n d , th e r e f o r e , r e d u ce s po w e r is th e s a m e as an l/m r a tio o f 0.25. t h us, a n y r m rc ic 2 / b c o nsu m e d in su bs e q u e n t st age s . i t shou l d a l s o b e note d t h a t t h er e is m o r e t h a n on e wa y t o get t h e de cima t i on b y 4. a decima tio n o f 4 in teg e r com b ina t io n o f l/m tha t yie l ds 0.25 w o rks (1/4, 2/8, o 4/16). h o w e v e r , fo r t h e b e st d y na mic ra n g e , us e t h e si m p les t ra tio . f o r exa m p l e , 1/4 g i v e s bet t er p e r f o r ma n c e tha n 4/16. table 14. ssb r c ic2 alias rejection table ( f f f l rc ic 2 ? 50 db ? 60 db ? 70 db ? 80 db ? 90 db ? 1 0 0 d 2 1. 79 1. 007 0. 566 0. 318 0. 179 0. 1 0 1 3 1. 508 0. 858 0. 486 0. 274 0. 155 0. 0 8 7 4 1. 217 0. 696 0. 395 0. 223 0. 126 0. 0 7 1 5 1. 006 0. 577 0. 328 0. 186 0. 105 0. 0 5 9 6 0. 853 0. 49 0. 279 0. 158 0. 089 0. 0 5 7 0. 739 0. 425 0. 242 0. 137 0. 077 0. 0 4 4 8 0. 651 0. 374 0. 213 0. 121 0. 068 0. 0 3 8 9 0. 581 0. 334 0. 19 0. 108 0. 061 0. 034 10 0. 525 0. 302 0. 172 0. 097 0. 055 0. 031 11 0. 478 0. 275 0. 157 0. 089 0. 05 0. 0 2 8 12 0. 439 0. 253 0. 144 0. 082 0. 046 0. 0 2 6 13 0. 406 0. 234 0. 133 0. 075 0. 043 0. 0 2 4 14 0. 378 0. 217 0. 124 0. 07 0. 04 0. 0 2 2 15 0. 353 0. 203 0. 116 0. 066 0. 037 0. 0 2 1 16 0. 331 0. 19 0. 109 0. 0 6 1 0. 035 0. 02 decima tion and inte rpol a t ion registers rci c 2 decima tio n val u es a r e sto r ed in reg i s t er 0x90. t h i s 1 r e g i s t er co n t a i ns t h e de c i m 2 - b i t a t i on val u e min us 1 . th e in t e r p ola - tio n p o r t io n is st o r ed in regis t er 0x91. t h is 9-b i t val u e h o lds t h e i n t e r p ol a t ion val u e min us on e . rcic2 sc ale register reg i st er 0x92 co n t a i n s t h e s c alin g inf o r m a t ion f o r th e rci c 2. the p r ima r y f u n c t i on is t o s t o r e t h e s c ale val u e co m p u t e d in t h e p r e v io us s e c t ion s . b i ts 4C0 o f t h is r e g i s t er sh o u ld b e wr i t t e n wi t h t h e s a me val u es as t h os e wr i t te n to bi ts 9C5 to a cco mm o d a t e a re d u ndan t in ter n a l ha r d war e fe a t ur e. b i ts 9C5 (s rci c 2 ) co n t a i n t h e 5-b i t scalin g fact o r f o r rci c 2. b i ts 11C10 a r e res e r v ed an d m u s t b e wr i t ten lo w . i n a p plic a t io n s t h a t do n o t r e q u i r e t h e fe a t ur es of t h e rci c 2, b y p a s s i t b y s e t t in g the l/m r a tio t o 1/1. t h is ef f e c t i v e l y b y p a s s es al l cir c ui t r y o f t h e rci c 2 excep t t h e s c alin g, w h ich is st i l l e f fe c t u a l.
ad6652 rev. 0 | page 37 of 76 e r i o n , fifth-order cic fil t er the fo ur t h sig n al p r o c es sin g st a g e , ci c5, im p l em e n ts a s h a r p fi x e d - c o e ffi c i e n t , d e c i m a t i n g fi l t e r t h a n r c i c 2 . t h e i n p u t r a t e t o t h is f i l t er is f sam p 2 . th e max i m u m in p u t r a te is g i ven b y t h e f o l l ow i n g e q u a t i on . n ch e q uals tw o f o r di v e rsi t y c h a n n e l r e al in p u t m o de; o t her w is e , n ch e q ual s o n e . t o sa ti s f y th i s eq u a t in cr e a s e m rci c 2 or re d u c e n ch . ch clk samp n f f 2 t h e d e cim a ti o n ra ti o , m ci c5 , ca n be p r og ra m m e d f r o m 2 t o 32 (al l in t e ger val u es). th e f r e q ue nc y r e s p o n s e o f t h e f i l t er is g i v e n b y t h e fol l o w in g e q u a t i o n s. u s e t h es e e q u a t i o n s t o calc u l a t e t h e ga in and p a ss- b a n d dr o o p o f cic5. b o t h p a r a meters can b e co m p en s a t e d f o r in the r c f s t ag e . 5 1 5 1 1 2 1 ) ( 5 5 ? ? ? ? ? ? ? ? ? ? = ? ? + z z z h cic cic m s 5 2 2 5 5 sin sin 2 5 ? ? cic 1 ) ( ? ? = f h ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + samp cic s f f f f m t ion wi t h o u t cr e a t i n g an ? ? samp the s c ale f a c t o r , s ci c5 , is a p r o g rammable u n sig n e d i n teger betw een 0 an d 20. i t s e r v es t o co n t r o l th e a t t e n u a t io n o f th e da t a in t o t h e cic5 s t a g e i n 6 db i n crem e n ts. f o r t h e b e s t d y namic ra n g e , set s ci c5 to t h e le ast a t t e n u a o v erf l o w co n d i t io n. this ca n be s a f e l y acco m p lis h e d usin g t h e f o l l ow i n g e q u a t i on , w h e r e ol rcic2 is t h e l a rg es t f r ac t i o n o f f u l l s c ale p o s s ib le a t t h e i n p u t t o t h i s f i l t er s t a g e . this val u e is o u t p u t f r o m th e rci c 2 s t a g e , t h en p i p e l i n e d in t o t h e ci c5. ( ) ( ) 5 log 2 5 5 2 5 ? = rcic cic cic ol m ceil s () 2 5 5 5 5 5 2 rcic s cic cic ol m ol cic = + the o u t p u t r a t e o f t h is s t a g e is g i v e n b y t h e fol l o w i n g e q ua t i on: 5 2 5 cic samp samp m f f = cic5 re jec t ion t a b l e 15 lis t s t h e a m o u n t o f b a n d wi d t h in p e r c en t a g e o f t h e in p u t ra te t h a t c a n be p r o t e c t e d wi t h va r i o us de cima t i on ra t e s a n d a l ias r e j e c t i o n sp e c if ic a t io ns. th e maxim u m in p u t ra t e i n to t h e c i c5 is 65 mh z w h en t h e rci c 2 de cima t e s b y 1. a s in t h e p r e v io us rci c 2 t a b l e ( t ab le 14), t h es e a r e t h e si n g le-sideb and b a ndwi d t h cha r ac ter i st ics o f t h e ci c5. h e f a n u p pe r bo un d o n d e c i ma ti o n , m ci c5 . table 15. ssb cic5 alias rejection table (f sa mp 2 = 1) m ci c5 ?50 db ?60 db ?70 db ?80 db ?90 db ?100 db the ci c5 st a g e ca n p r o t e c t a m u ch wi der b a n d t o a n y g i v e n re j e c t i o n t h a n r c ic 2 . g i v e n t h e desire d f i l t er cha r ac ter i s t ics, t a b l e 15 ca n he l p in t c a l c ul a t i o n o 2 10. 27 7 8. 078 6. 393 5. 066 4. 008 3. 183 3 7. 924 6. 367 5. 11 4. 107 3. 297 2. 642 4 6. 213 5. 022 4. 057 3. 271 2. 636 2. 121 5 5. 068 4. 107 3. 326 2. 687 2. 17 1. 748 6 4. 267 3. 463 2. 808 2. 27 1. 836 1. 48 7 3. 68 2. 989 2. 425 1. 962 1. 588 1. 281 8 3. 233 2. 627 2. 133 1. 726 1. 397 1. 128 9 2. 881 2. 342 1. 902 1. 54 1. 247 1. 007 10 2. 598 2. 113 1. 716 1. 39 1. 125 0. 909 11 2. 365 1. 924 1. 563 1. 266 1. 025 0. 828 12 2. 17 1. 765 1. 435 1. 162 0. 941 0. 76 13 2. 005 1. 631 1. 326 1. 074 0. 87 0. 703 14 1. 863 1. 516 1. 232 0. 998 0. 809 0. 653 15 1. 74 1. 416 1. 151 0. 932 0. 755 0. 61 16 1. 632 1. 328 1. 079 0. 874 0. 708 0. 572 17 1. 536 1. 25 1. 016 0. 823 0. 667 0. 539 18 1. 451 1. 181 0. 96 0. 778 0. 63 0. 509 19 1. 483 375 1. 119 0. 91 0. 737 0. 597 0. 20 1. 307 1. 064 0. 865 0. 701 0. 568 0. 4 5 9 21 1. 245 1. 013 0. 824 0. 667 0. 541 0. 4 3 7 22 1. 188 0. 967 0. 786 0. 637 0. 516 0. 4 1 7 23 1. 137 0. 925 0. 752 0. 61 0. 494 0. 3 9 9 24 1. 09 0. 887 0. 7 2 1 0 . 584 0. 474 0. 383 25 1. 046 0. 852 0. 6 9 2 0 . 561 0. 455 0. 367 26 1. 006 0. 819 0. 666 0. 4 3 5 0. 437 0. 3 5 2 7 0. 969 0. 7 8 9 0 . 641 0. 5 2 0. 421 0. 34 28 0. 934 0. 761 0. 618 0. 501 0. 406 0. 328 29 0. 902 0. 734 0. 597 0. 484 0. 392 0. 317 30 0. 872 0. 71 0. 577 0. 468 0. 379 0. 306 31 0. 844 0. 687 0. 559 0. 453 0. 367 0. 297 32 0. 818 0. 666 0. 541 0. 439 0. 355 0. 287 ?150 ?130 ?110 ?90 ?70 ?50 ?30 ?10 ?2 ? 1 0 1 2 +1 0 db mu l t i p l e s o f c i c 5 o u t pu t r a t e 03198-0-035 f i gure 48. d o ub le s i de-b and g r ap h sh o w ing cic5 f i lter r e sp onse and a l ias r e jec t ion of ? 1 0 0 d b
ad6652 rev. 0 | page 38 of 76 d e , o n e t a p fo r i a n d on e t a p fo r q ram coefficient fil ter the f i nal sig n al p r o c es sin g s t a g e is a s u m-o f -p r o d u c t s de cima t - in g f i l t er wi t h pr og ra mma b l e co ef f i cien ts. a si m p lif i e d b l o c k di a g r a m is sh ow n in f i gur e 49. the da t a m e mo r i es i-r a m a n q-ram s t o r e t h e 160 m o s t r e c e n t com p lex s a m p les f r o m th p r e v io us f i l t er st a g e wi t h 20- b i t r e s o l u t i o n . th e co ef f i cien t m e m o r y , cmem, s t o r es u p t o 256 co ef f i cien ts wi t h 20-b i t r e s o l u t i o n . on e v er y clk c y c l e a r e calc u l a t e d u s in g t h e s a m e c o ef f i cien ts. th e r c f o u t p u t co n s is ts o f 24 b i ts o f i da ta and 24 b i ts o f q da t a . 160 20b i-ram i in i out 256 20b c-ram 160 20b q-ram q in q out 03198-0-036 f i gu r e 4 9 . r a m c o effi c i en t f i l t er bl oc k di a g r a m rcf dec i ma tio n r e gis t er u s e e a ch rcf cha n n e l t o de cima t e t h e da t a ra te. th e de cima - tio n r e g i s t er is an 8-b i t r e g i s t er t h a t c a n decima te f r o m 1 t o 2 5 6 t h e r c f dec i ma tio n is s t o r e d in 0xa0 in t h e f o r m o f m . 1 . ap p l i c at i o n , t w o r c f f i l t e r s w o u l d b e p r o c e s s i n g t h e s a m e d a t a e o f 2 . rc f ? the i n p u t r a t e to t h e r c f is f samp5 . rcf dec i ma tio n ph ase u s e t h e r c f de cima t i on phas e t o syn c hr o n i z e m u l t i p le f i lt ers wi t h in a ch i p . this is us ef u l w h en usin g m u l t i p le cha n n e ls wi t h in t h e ad6 652 t o im p l em en t a p o l y p h as e f i l t er , r e q u ir in g t h a t t h e r e s o ur c e s o f s e v e ral f i l t ers be p a ral l e l e d . i n s u c h an f r o m t h e cic5. h o w e v e r , e a ch f i l t er is dela ye d b y o n e-half t h decima tio n r a t e , th us cr ea tin g a 180 p h as e dif f er en ce betw een th e tw o hal v es. the ad6652 f i l t er c h a nne l us es th e va l u e s t o r e d in t h is r e g i st er to p r e l o a d t h e rcf co un t e r . th e r efo r e , in s t e a d s t a r ti n g f r o m 0, th e co un t e r i s loa d ed wi th th i s val u e , th u s cr ea tin g an o f fs et in t h e p r o c es si n g t h a t sh o u ld be e q ui vale n t t o th e r e q u ir e d p r o c es sin g de l a y . t h is da ta is st o r ed in 0xa1 as an 8-b i t n u m b er . rcf f i l t er l e ngth the maxi m u m n u m b er o f t a ps t h is f i l t er can ca lc u l a t e , n ta p s , i s g i v e n b y t h e fol l o w in g e q u a t i o n . the val u e n ta p s ? 1 i s wr i tte n t o th e c h ann e l r e g i s t er wi thin t h e ad6652 a t addres s 0 x a ? ? ? ? 5 samp f h e r e min in dica t e s t h ? ? 160 , min rcf taps n w a t n ta p s i s t h e les s er o f t h e tw o val u es, t h e e n ts n e e d n o t b e sy mm et r i c, a n d t h e co ef f i cien t len g t h , n ta p s , ca n b e e r o d d . i f t h e co ef f i cien ts a r e symm et r i c, t h p o n s e m u s t b e wr i t t e n in t o t h e co ef f i cien t r a m. ts is onl y 128 w o r d s e s, da ta f r o m t h e ci c5 in t o a 160 40 ram. f i c i en t addr es s r c f off + n ta p s ? 1 is r e ac h e d . ? ? se pa ra t e d b y th e co m m a , tha t a p pea r w i th in t h e b r a c k e t s . the r c f co ef f i cien ts a r e lo ca t e d in addr es s e s 0 x 00 t o 0x7f a n d a r e in t e r p r e t e d as 20-b i t tw os c o m p le m e n t n u m b ers. w h en wr i t i n g t h e co ef f i cien t r a m, t h e lo w e r addr es s e s a r e m u l t i p li e d b y r e la t i vely older da t a f r o m t h e ci c5, an d t h e hig h er co ef f i - cien t addr es s e s a r e m u l t i p li e d b y r e la t i ve ly ne wer da t a f r o m ci c5. th e co ef f i c i v en o e n b o t h sides o f t h e i m p u ls e r e s al th o u g h the b a s e m e m o r y f o r co ef f i c i e n lo n g , th e ac t u al len g th is 256 w o r d s lo n g . th er e a r e tw o p a g eac h o f 128 w o r d s lo n g . th e p a g e is s e lec t e d b y b i t 8 o f 0 x a 4 . al th o u g h th i s da ta m u s t be w r i t t e n in pa g e s , t h e i n t e rn al co r e ha ndles f i l t ers tha t exceed t h e l e n g th o f 128 ta ps. th er ef o r e , the full le n g th o f th e da t a ra m ca n b e us e d as t h e f i l t er len g t h (160 ta ps). the r c f st o r es th e 160 20 is as sig n e d t o i da t a and 160 20 is as s i g n e d t o q da ta . the r c f us es t h e r a m as a cir c u l a r b u f f er , s o tha t i t is dif f i c u l t t o k n o w i n w h ich addr ess a p a r t ic u l a r da t a e l e m en t is st o r e d . w h en t h e rcf calc u l a t es a f i l t er o u t p u t , i t s t a r ts b y m u l t i p l y in g t h e oldes t val u e in t h e da t a r a m b y t h e f i rs t c o ef f i cien t, which is p o in t e d t o b y t h e rcf co ef f i cien t o f fs et r e g i s t er (0xa3). t h i s val u e is acc u m u la ted wi th t h e p r o d uc ts o f new e r da t a w o r d s m u l t i p li e d b y t h e s u b s e q u en t lo ca t i on s i n t h e c o ef f i cien t r a m un t i l t h e co e f table 16. thre e-tap filter coefficient address impulse response data 0 h(0) n ( 0 ) o l d e s t 1 h(1) n ( 1 ) 2 = (n taps ? 1) h(2) n ( 2 ) n e w e s t the r c f co ef f i cien t o f fs et r e g i s t er has tw o p u r p os es. t h e m a p u r p os e o f this r e gis t er is f o r ra p i d f i l t er c h an ges, b y al l o w i n m u l t i p le f i l t er s to be lo aded in t o m e m o r y a n d t h en s e lec t ed i n g h is f sim p ly b y cha n g i n g t h e o f fs et as a p o i n t e r . th e ot h e r us e o f t r e gis t er is t o f o rm p a r t o f sym b o l tim i n g ad j u s t m e n t . i f t h e desir e d f i l t er le n g t h is p a dde d wi t h zer o s o n t h e en d s , t h e n t h e s t a r tin g p o in t c a n be ad j u s t e d to f o r m s l ig h t dela ys in w h en the f i l t er is co m p u t e d wi t h r e fer e n c e t o t h e hig h s p e e d clo c k. this allo ws f o r v e r n ier ad j u s t m e n t o f th e sy m b o l tim i n g . c o ur se a d j u s t m e n t s ca n b e m a de wi th th e r c f d e ci ma ti o n p h a s e . t h e o u t p u t r a t e o f this f i l t er is det e r m in ed b y t h e o u t p u t ra t e o t h e c i c5 s t a g e a n d m rc f , a s f o l l o w s : rcf samp sampr m f f 5 =
ad6652 rev. 0 | page 39 of 76 b i ts 4 an d 5 deter m in e t h e ou t p u t mo . m o de 00 s e ts the c h i p u p in f i x e d-p o in t m o de . th e n u m b e r f b i ts is det e r m in e d b y l p o rt c o n f i g u r a t i o n . d 4 . i n t h is m o de , an ( x i s t o u t p ut mode form ats format value rcf ou tpu t sc ale f a c t or an d c o ntrol register reg i st er 0xa4 is a co m p o u nd r e gis t er us ed t o c o nf igur e s e v e ral as p e c t s o f t h e rcf r e g i s t er . u s e b i ts 3C0 t o s e t t h e s c ale o f t h e f i xe d-p o i n t o u tp u t m o de. this s c a l e va l u e ca n a l s o b e us e d to se t th e f l oa ti n g -po i n t o u t p u t s in co n j u n ct i o n wi th b i t 6 o f th i s re g i ste r . de o t h e s e ri a m o e 0 1 s e lec t s f l o a tin g -p o i n t m o d e 8 + 8 - b i t m a n t is s a is f o l l o w ed b y a 4-b i t exp o n e n t . i n m o d e 1 x do n t c a r e ), th e m o de is 12 + 4, o r 12-b i t man t iss a an d 4 - b i exp o n e n t . t a b l e 1 7 . floating point 12 + 4 1x floating point 8 + 4 01 fixed point 00 n o r m al l y , th e ad6652 det e r m in es t h e exp o n e n t val u e tha t o p t i mi zes n u m e r i ca l acc u r a c y . h o w e v e r , if bi t 6 is s e t, t h e va l u e s t o r ed in b i ts 3 C 0 is us ed t o s c a l e th e o u t p u t . this en s u r e s c o ns i s te n t s c a l i n g a n d a c c u r a c y d u r i ng c o n d it i o ns t h a t m i g h t wa r r a n t p r e d ic t a b l e o u t p u t ra ng es. i f b i ts 3C0 ar e r e p r es en t e d b y r c f s c a l e , t h e s c a l in g fac t o r in db is g i v e n b y db ) 2 ( log 20 ) 3 ( 10 ? = f o r a n r c f s c al e o f 0, th e s c aling fac t o r is eq ual t o ?18.06 db , and fo r a max i m u m rcf s c a l e o f 15, t h e s c a l ing f a c t o r is e q ua l t o +72.25 db . i f b i t 7 is s e t, t h e s a m e exp o n e n t is us ed f o r bo t h the r e al an d r y (i a n d q) o u t p u t s. th e exp o n e n t us e d is t h e on e t h a t p r e v en ts n u m e r i c o v erf l o w a t t h e exp e n s e o f smal l sig n al m a p r o b lem , b e ca us e sm al l b i t 8 is t h e r c f b a nk s e le c t b i t us e d t o p r og ra m t h e r e g i s t er . n o te d t h a t whi l e t h e chi p is com p u t in g f i l t ers, p u t l e l 1 ca n a l s o b e p a ir e d w i t h c h a n ne l 0. this co n t r o l b i t is 6 5 2 c h a nne l o p er a t es in n o r m al m o de . h o w e v e r , if b i t 10 is s e t, th en t h e r c f is b y p a s s ed t o cha n ne l b i st e e t h e u s er -c o n f i gura b l e b u i l t-i n s e lf- t e s t (b ist) ima g i n a acc u rac y . h o w e v e r , this is s e ldo n u m b ers w o u l d r e p r es en t 0 r e g a r d les s o f t h e ex p o n e n t us e d . w h en this b i t is 0, th e lo w e s t b l o c k o f 128 is s e l e c t ed (t a p s 0 t o 127). w h en hig h , th e hig h es t b l o c k is s e lec t ed ( t a p s 128 t o 255). i t s h o u ld b e t a p 127 is ad jac e n t t o t a p 128 and th er e a r e n o p a g i n g is s u es. b i t 9 s e le c t s w h er e t h e i n p u t t o e a ch r c f o r ig i n a t es. i f b i t 9 is cle a r , t h en t h e rcf in p u t com e s f r o m t h e cic5 n o r m al ly a s soci a t e d wi th th e r c f . h o w e v e r , i f th e b i t i s set , th en th e i n co m e s f r o m ci c 5 ch a n n e l 1. t h e o n l y e x ce p t i o n i s ch a n n e l 1, wh i c h uses t h e o u t p u t o f c i c 5 ch a n n e l 0 as i t s al t e rn a t e . u s in g th i s f e a t u r e , ea ch r c f ca n ei th er o p e r a t e o n i t s o w n c h a n n e da ta o r be p a ir e d wi th t h e r c f o f cha nne l 1. th e rcf o f c h a n n us e d wi t h p o ly phas e di st r i b u te d f i l t er in g. i f b i t 10 is c l ea r , th e a d 6 . s secti o n f o r m o r e d e ta il s .
ad6652 rev. 0 | page 40 of 76 p o l a t ing ha lf-band fil ters a t n d f o ll o w th e f o ur s i t q t o th e a g c. the half-band an d a g c o p era e i n de p e nden t l y o f e a ch ot h e r , s o t h e a g c can b e , in w h ic h cas e t h e o u t p u t o f th e half -ba n d is s e n t t o t h e ou t p u t da t a p o r t . the half-b and f i l t ers als o er o n e can b e ena b le d a t a d dr ess a f t h e e t h o d s: h a nne ls o f th e ad6652 a r e us ed t o p r o c es s e by o h a n n e l 2. e a c h half-ba n d in t e rle a v e s i n t e r the ad6652 has tw o in t e r p ola t in g half-band f i r f i l t e r s t h imm e dia t e l y p r eced e t h e tw o digi tal a g c s a r c f c h a n n e l o u t p u t s. e a ch in t e r p ola t in g half -b a n d ta k e s 16-b i t i a n d 1 6 - b i t q da t a f r o m th e p r ec edin g rcf a n d o u t p u t 16-b i t i and 16-b t b y p a s s ed dir e c t l y o p e r a t e i n de p e nden t l y o f e a ch ot h e r e i t h o r dis a b l e d . t h e co n t r o l r e g i ster fo r h a lf-b a n d a i s 0x08 a n d f o r h a lf-b an d b is a t a ddr es s 0x09. h a lf-b and f i l t ers als o p e r f o r m th e f u n c t i on o f in t e rle a v i n g da t a f r om v a r i ou s rc f ch an nel output s pr i o r to t h e a c tu a l f u nc t i o n o f in t e r p ola t io n. i n t e rle a v i n g o f da t a is a l lo w e d e v en w h e n t h e half-b an d f i lt er is b y p a s s e d . thi s al lo ws t h e im plem e n t a t i o n o f p o lyphas e f i l t er b y co m b ini n g t h e p r o c e s sin g p o w e r o f m u l t i p l e c h a n n e ls t o ac t u p o n a sin g le c a r r i er . this is acco m p lish e d b y a p p r o p r i a t e phasin g o f t h e p r o c es sin g cha n ne ls usin g o n e o fol l o w ing m ? rc f pha s e d e c i ma t i on ? st ar t ho l d - o f f c o u n te r f o r exa m p l e , if tw o c o n e c d ma200 0 ca r r i er , r c f f i l t ers fo r b o t h t h e cha n n e ls s h o u ld b e 180 o u t o f p h as e . this ca n be don e usin g r c f p h as d e c i m a t i on or a n a p propr i ate st ar t ho l d - o f f c o u n te r f o l l owe d a p p r o p r i a t e n c o phas e o f fs ets. h a lf-band a can lis t en t o al l f o ur c h a nne ls: cha nne ls 0, 1, 2, a n d 3; cha nne l 0 and 1; o r o n l y cha nne l 0. h a lf-b and b can lis t en t cha n n e ls 2 an d 3, o r o n l y c t h e chann e ls sp e c if ie d i n i t s con t r o l r e g i st er and in t e r p ola t es b y t w o on t h e c o mbi n e d d a t a f r om t h o s e ch an n e l s . f o r one ch an ne l r u nnin g a t t w ic e t h e chi p ra t e , t h e half- b an d can b e us e d t o o u t p u t c h a n n e l da ta a t f o u r tim e s th e c h i p ra t e . t h e f r eq u e n c y re sp ons e of t h e i n te r p o l a t i n g h a l f - b a n d f i r i s s h ow n i n f i gur e 50. multiples of chip rate 0 1.0 2.0 3.0 3.5 4 . 0 ?7 0 ?8 0 0.5 1.5 2.5 i n 3 f samp 0 s p e c t r u m o f h a l f - b a n d db ( | spec tr u m _c oef|) ?2 0 ?4 0 ?1 0 ?3 0 ?5 0 ?6 0 f samp f chip f chip 03198-0-037 f i gure 50. inte rpo l ating ha lf-ba n d f r equenc y r e s p ons e the s n r o f the in t e r p ol a t in g ha lf-ban d is a r o u nd ?149.6 db . the hig h est er r o r s p urs d u e t o f i xe d-p o i n t a r i t hm et ic a r e a r o u n d ?172.9 db . th e co ef f i cien ts o f the 13-t a p in t e r p ol a t ing ha lf-b a n d fir ar e g i v e n i n t a b l e 18. table 18. half- b and co efficie n ts 0 14 0 ? 66 0 309 512 309 0 ? 66 0 14 0
ad6652 rev. 0 | page 41 of 76 g a in r . g c r e ject n l y f h e h e a g c s t r i v e s t o ma in t a in a co n s t a n t m e an m u l t i p li er . : u n c a t i on of bit s b e l o w t h e output r a nge. o v e r f l ow i s c a u s e d by p p i ng er r o rs when t h e o u t p u t sig n al exce e d s t h e o u t p u t ra n g e . m o d u l a t i on er r o r o c c u rs wh e n t h e o u t p u t ga in va r i es d u r i n g t h e re c e pt i o n of d a t a . s e t t h e desir e d sig n a l le vel b a s e d o n t h e p r ob ab i l i t y - den s ity f u n c t i on o f t h e sig n al, s o t h a t t h e er r o rs d u e t o un der f lo w a n d o v erf l o w a r e b a la n c e d . s e t t h e ga in and dam p ing val u es o f t h e lo o p f i l t er s o tha t t h e a g c is fas t en o u gh t o trac k lo n g -t er m a m pli t ude v a r i a t io n s o f t h e sig n al t h a t mig h t c a us e exces s i v e u n d e r f l o w or ove r f l ow , but sl ow e n ou g h to a v oi d e x c e ss ive l o ss o f a m pli t ude info r m a t io n d u e to t h e m o d u l a t i on o f t h e sig n al. a g c l oop the a g c lo o p is im p l em en t e d usin g a log-lin e a r a r c h i t ec t u r e . i t p e r f o r m s f o ur basic o p era t ion s : p o w e r calc u l a t io n, er r o r calc u - la tio n , lo o p f i l t er in g, a n d ga in m u l t i p lica t i o n . the a g c can b e co nf igur e d t o op era t e in one o f t h e fol l o w in g m o de s: ? desir e d sig n al l e v e l m o de ? desir e d c l i p p i ng lev e l m o de as s e t b y b i t 4 o f a g c co n t r o l w o r d (0x0a, 0x12) the a g c ad j u s t s th e ga in o f the in comin g da t a acco r d in g t o h o w fa r i t s lev e l is f r o m th e desir e d sig n al leve l o r desir e d cl ippi n g l e v e l, d e p e nd i n g on t h e mo d e of op e r at i o n s e l e c t e d . n h automa tic gain control the ad6652 is eq ui p p ed wi th tw o in dep e n d en t a u t o ma t i c co n t r o l (a gc) lo o p s fo r dir e c t in ter f ace wi t h a r a k e r e cei v e e a c h a g c cir c u i t has 96 db o f ra n g e . i t is im p o r t a n t tha t t h e d e ci ma ti n g f i l t er s o f th e a d 6652 p r eced i n g th e a t w o da t a p a t h s to t h e a g c lo o p a r e p r o v ide d : on e b e fo r e t h e c l ippi n g c i rc u i t r y and o n e af te r t h e c l ippi ng c i rc u i t r y , a s s h o w i n fi g u r e 5 1 . fo r d e s i r e d s i g n a l l e v e l m o d e , o n l y t h e i / q p a t befo r e t h e c l i p p i n g is us e d . f o r desir e d c l i p p i n g le v e l m o de , t h e dif f er en ce o f t h e i/q sig n als b e fo r e a n d a f t e r t h e cli p p i n g cir c ui t r y is us e d . un desir e d sig n a l s, s o t h a t e a c h a g c lo o p is o p era t in g on o th e c a rri e r o f i n t e r e s t a n d c a rri e r s a t o t h e r f r eq u e n c i e s d o n o t a f f e ct th e ra n g in g o f th e loo p . the a g c com p r e s s es t h e 23 -b i t co m p lex o u t p u t f r o m t h e in t e r p ol a t i n g ha lf-b an d f i l t er in to a p r og ra mma b l e w o r d si ze o 4 t o 8, 10, 12, o r 16 b i ts. b e c a us e th e smal l sig n al s f r o m th e lo w e r b i ts a r e p u s h e d in t o hig h er b i ts b y adding ga in, the cli p p i ng o f t h e l o w e r b i ts do es no t co m p r o mis e t h e snr o f t sig n al o f in t e r e st. t clip i 23 bits q clip mean square (i + jq) gain m u l t i p l i e r i p r o g r a m m q u s e d o n l y f o r desired c l i p p i n g l e v e l mode ? ? 2 x o u t p ut p o w e r desp i t e in p u t sig n a l f l uc t u a t io n s . this p e r m i t s o p era t ion i n e n vir o nm e n ts w h e r e t h e dyna mic ra n g e o f t h e sig n al exce e d s t h e d y na mic ra ng e o f t h e o u t p u t r e s o l u t i o n . the a g c s an d t h e i n t e r p ol a t ion f i l t ers n e e d n o t b e li n k e d t o g e t h er . ei t h er ca n b e s e le c t e d wi t h o u t t h e o t her . th e a g c s e c t io n ca n b e b y p a ss e d , if desire d , b y s e t t in g bi t 0 o f t h e a g c c o n t ro l word. w h e n by p a s s e d , t h e i / q d a t a i s st i l l cl ipp e d to a desir e d n u m b er o f b i ts, and a con s t a n t ga i n can b e p r o v i d e d th r o u g h th e a g c g a i n average 1 ? 16384 samples decimate 1 ? 4096 samples square root k z ?1 1 ? (1 + p) z ?1 + p z ?2 error k gain p pole + ? r desired a b l e bit width log 2 (x) 03198- 0- 038 desired signal le vel mode i n t h is m o de o f o p era t ion, t h e a g c st r i v e s t o ma in t a in t h e output s i g n a l at a pro g r a m m a bl e s e t l e v e l. t h i s mo d e of op e r a- tio n is s e lec t e d b y wr i t in g a g c co n t r o l w o r d (0x0a:4, a n d 0x12:4) t o log i c 0. f i rs t, th e lo op f i n d s t h e s q uar e (o r p o w e r) o f th e in co m i n g co m p le x da ta s i g n al b y sq u a ri n g i a n d q a n d addi n g t h em. this o p era t ion is im ple m e n t e d i n exp o n e n t ia l do ma in usin g 2 x . the a g c lo o p has a v er a g e and de cima t e b l o c ks t h a t o p er a t e on po w e r sa m p l e s be f o r e th e sq ua r e r o o t o p e r a t i o n, a s s h o w n in f i gur e 51. th e a v era g e b l o c k can b e p r og ra mme d t o a v era g e 1 t o 16,384 p o w e r s a m p les, a n d th e decima t e b l o c k can be p r o- g r a m m e d t o u p da t e t h e a g c on ce ev er y 1 t o 4096 s a m p les. the limi t a t i o n s o n t h e a v era g i n g o p era t io n a r e t h a t t h e n u m b er o f a v e r age d p o we r s a m p l e s m u s t b e an i n t e ge r m u lt i p l e of t h e de cima t i o n v a l u e , a n d t h e o n ly al lo wa b l e m u l t i p le val u es a r e 1, 2, 3, o r 4 . the a v er a g in g and de cima t i on e f fe c t i v e l y m e an t h a t t h e a g c ca n op era t e o v er a v era g e d p o w e r o f 1 t o 16,384 o u t p u t s a m p les. the ch o i ce o f u p da tin g t h e a g c o n c e ev er y 1 to 4096 s a m p les a n d o p er a t in g on a v er a g e p o w e r faci li t a t e s t h e i m ple m en t a t i on o f a lo o p f i l t er wi t h s l o w t i m e co n s t a n t s, w h ere t h e a g c er r o r co n v erg e s s l o w ly a n d ma k e s inf r e q uen t ga in ad j u s t m e n t s. i t w o u l d als o b e u s e f u l w h er e t h e us er wa n t s t o k e ep t h e ga i n s c a l in g con s t a n t o v er a f r a m e o f d a t a (o r a st r e am o f sy m b ols). f i g u re 51. bl ock d i ag r a m of t h e a g c thr e e s o ur ces of er r o r ca n b e in t r o d uce d b y t h e a g c f u n c t i o n u n d e r f l o w , ove r f l ow , and mo d u l a t i on . u n d e r f l o w i s c a u s e d by t r cli
ad6652 rev. 0 | page 42 of 76 t p u t a - g i sters. b i t g r o w t h ass o c i a t e d w i t h c i c f i lters dep e n d s on un ts fo r t h e divisio n ass o c i a t e d w i t h a in c t o p era t ion, o n ly co a r s e s c a l in g is p o ssi b le . f i n e s c a l in g is i m ple- n s e c t i 1 4 u o r t co n t r o l i ste wher o 4096). a m p les p r og ra mme d as a i m o r 4). a thc a d - g u p t o t b e r . x a m p l e , if a a tio n ra tio m cic i s 1 d n av g is t e d t o be 3 (decima t io n o f 1000 a n d a v g o f 3000 a m p les), t h e n t h e ac t u a l ga in d u e t o a v era g i n g a n d de ci ma t i o n 3 0 0 0 o r 69.54 db ( = log 2 (3000)). b e ca us e a t t e n u a t io n is if t o p er a t io n, o n ly m u l t i p les o f 6.02 db g is u t p u t f r o m t h e a v er- a a p p l i ng a sim p b - t r ac t e d f r o m t h e r e q u es t sig n al le v e l, r , sp e c if ie d in r e g i st ers (0x0b , 0x14), lea v in g an er r o r t e r m t o be p r o c es s e d b y t h e lo o p fi l t e r , g(z) . r og ra mma b l e r e q u est sig n al le v e l, r , acco r d in g t o t h e t sig n al le v e l desir e d . the r e q u es t sig n al le v e l r is r e q u f a n y , d u e t o t h e r e q u l is o f fs et b y t h e am o u n t o f er r o r in d u ce d i n c, b e ca us e t h e n u m b er o f a v era g e s a m p les m ust b e a n i n teg e r m u l t i p le o f t h e decima tio n val u e , o n l y th e m u l t i p le n u m b er 1, 2, s e t t h is p o u t p u 3, o r 4 is p r ogra m m e d . this n u m b er is p r ogra m m e d i n o u p o r t c o n t r o l reg i s t ers 0x10:1C0 a n d 0x18:1C0. th es e a v era g e d s a m p les a r e t h e n de cim a te d w i t h de cim a t i on r a t i o s p r o g r a m m b l e f r o m 1 t o 4096. this 12-b i t decima tio n r a tio is def i n e d i n reg i st ers 0x11 a n d 0x19. the a v er a g e and de cima te o p er a t io n s a r e l i n k e d t o g e t h er a n d im ple m e n te d usin g a f i rst - o r der ci c f i l t er and f i f o r e the ga i n an d th e deci ma ti o n ra ti o . t o co m p en sa t e f o r th e g a in a s s o cia t ed wi t h t h es e o p era t io n s , a t t e n u a t i o n s c a l in g is p r o v ide d b e fo r e t h e ci c f i l t er . this s c a l in g o p e r a t io n ac c o t h e v era g i n g op era t ion as we l l as t h e t r adi t io nal b i t g r o w t h ci f i l t ers. b e c a us e t h is s c a l ing is im p l e m e n t e d as a b i t shif m e t e d as an o f fs et in t h e r e q u es t leve l , exp l a i n e d l a t e r i n t h i s o n. the a t ten u a t ion s c a l i n g, s ci c , is p r o g r a mmable f r o m 0 to s i n g f o ur b i ts o f 0x10 a n d 0 x 18 o f th e o u t p u t p re g r s , an d i s g i ve n by )] ( [log 2 avg cic cic n m ceil s = e: m cic is t h e decima tion ra tio (1 t n av g is t h e n u m b er o f a v era g e d s m u l t i p le o f dec a tio n ra tio (1, 2, 3 , ceil is m s p ea k f o r r o u n d i n h e next wh o l e nu m f o r e d e c i m 0 0 0 a n s e lec er a g i n s i s im ple m e n t e d as a b i t sh a tte n u a t i o ns are p o ss ibl e . s ci c , in t h is cas e , is 12 c o r r esp o n d i n t o 72.24 db . this wa y , s cic s c aling al wa ys a t t e n u a t es m o r e tha n s u f f i cien t t o com p e n s a t e fo r t h e ga in chan g e s i n a v er a g e and de cima t e s e c t ion s an d , t h er efo r e , p r e v en ts o v er f l o w s in t h e a g c lo o p . bu t i t is a l s o e v iden t t h a t t h e c i c s c a l in g i s ind u cin g a ga in er r o r (dif fer e n c e b e tw e e n g a in d u e t o cic a n d a t ten u a t i o n prov i d e d ) of up to 6 . 0 2 d b . t h i s e r ror shou l d b e c o m p e n s a te d f o r i n th e r e q u es t si gn al lev e l , as exp l a i n e d b e lo w . l o ga r i t h m t o t h e b a s e 2 is a p pli e d t o t h e o a g e and de cim a te s e c t io n. th e s e de cim a te d p o wer s a m p les ( i n l o g r i t h mic do ma in) a r e con v e r t e d t o r m s sig n al s a m p les b y y i ng a s q u a re ro ot . t h i s s q u a re ro ot i s i m p l e m e n te d u s le s h if t o p e r a t io n. the r m s s a m p les s o ob t a in e d a r e su p r og ra mma b l e f r o m 0 t o ?23.99 db in s t eps o f 0 . 094 db . th e e s t s i gn al l e v e l s h o u l d al so c o m p en sa t e f o r e r r o r , i e c i c s c ali n g, as explaine d p r e v io us ly . th e r efo r e , t h es t sig n al le v e ci g i v e n b y 02 . 6 ) ( log 20 10 ? = cic avg cic s n m offset w h r e t h e o f fs et is in db . e c n t in u i n g wi t h t h e p r e v io us e x a m ple , t h is o f fs et is g i v e n b y h o off s e t = 72.24 ? 69.54 = 2.7 db s o t e r e q u est sig n al le v e l is g i ven b y 094 . 0 ) ( ? ? ? ? ? = offset dsl ceil r 094 . 0 ? ? e: wher ds l desir ther efo r e , in t h e p r e v io us exa m ple , if t h e desir e d sig n al le ve l is ? 1 6 . the a g c p r o v i d es a p r og ra mma b l e s e cond-or d er lo o p f i l t er . def i n s u b t r o c es s e d b y t h e lo o p ga in e ra tio t h e pa ra r i s t h e r e q u es t sig n al le v e l. (desir ed sig n al lev e l) is t h e o u t p u t sig n al le v e l tha t t h e us er e s. ?13.8 db , th e r e q u es t sig n al leve l , r , i s pro g r a mme d to b e 5 4 d b . t h e p r ogra m m a b le pa ram e t e r s , ga in k and p o le p , c o m p l e t e l y e t h e lo o p f i l t er cha r ac t e r i s t ics. th e er r o r t e r m a f t e r r ac t i n g t h e r e q u es t sig n al le v e l is p fi l t e r , g(z) . th e o p en lo o p p o les o f t h e s e cond-or d er lo o p f i l t er are 1 an d p , r e s p e c t i v e l y . t h e l o o p f i l t e r p a r a m e t e r s , p o l e p a n d k , a l lo w ad j u st m e n t o f t h e f i l t er t i m e co nst a n t , w h ich det e r m i n es t h e wi n d o w fo r calc u l a t i n g t h e p e a k -t o-a v era g . o p e n lo o p t r a n sfer f u n c t i o n fo r t h e f i l t er , incl udin g t h e g a i n m e ter is as f o ll o w s: 2 1 ) 1 ( 1 ? ? + + ? pz z p i f t h e a g c is p r o p erly co nf igur e d (in t e r m s o f o f fs et in r e q u es t le v e l), t h e n t h ere a r e n o ga i n s e x cep t t h e f i l t er ga in k. u n der 1 ? kz ) ( = z g t h es e cir c ums t an ces, a clos e d lo o p exp r es sio n fo r t h e a g c lo o p is p o s s i b le and is g i v e n b y 2 1 1 ) 1 ( 1 ) ( 1 ) ( ) ( ? ? ? + ? ? + = + = pz z p k kz z g z g z g closed t h e ga in pa ra m e t e r k an d p o le p are pro g r a mmabl e t h rou g h r e g i s t ers (0x0e a n d 0x0f , r e s p ec ti v e l y , f o r a g c cha n n e l a and cha n n e l b) f r o m 0 t o 0.996 in s t eps o f 0.0039 usin g 8-b i t
ad6652 rev. 0 | page 43 of 76 le p s e d s p 1 , r e p r es en t a t i o n . th o u g h t h e us e r def i n e s t h e o p en lo o p p o an d g a i n k , th ey d i r e ctl y i m pa ct th e p l a c em en t o f th e c l o lo o p p o les a n d f i l t er c h a r ac t e r i stics. th es e c l os e d lo o p p o l e p 2 a r e t h e r o o t s o f t h e de n o mina t o r o f t h e ab o v e clos e d lo o p tra n s f e r fu n c ti o n a n d a r e gi v e n b y 2 4 ) 1 ( ) 1 ( , 2 2 1 p k p k p p p ? ? + + ? + = t y pi c a l l y t h e a g c l o op p e r f or m a n c e i s d e f i ne d i n te r m s of it s ti m e c o n s ta n t o r se t t l i n g t i m e . i n s u c h a c a se , set th e c l ose d po le s t o m eet th e tim e co n s ta n t s r e q u i r ed b y th e a g c loo p . th e f o l l ow i n g rel a t i on b e t w e e n t i m e c o nst a n t a n d c l o s e d l o op p o ca n be us e d f o r this p u r p os e: l o o p l e s ? ? ? ? ? = 2 , 1 exp m p cic ? ? ? 2 , 1 rate sample wher e: 1,2 a r e th e tim e co n s ta n t s co rr e s po n d i n g t o th e po le s p 1,2 . exp den o t e s t h e in v e rs e o f t h e na t u ral log. t h e t i me c o nst a n t s c a n a l s o b e d e r i ve d f r om s e tt l i ng t i me s a s fol l o w s: 3 % 5 4 % 2 time settling or time settling = wher e: m cic (ci c decima tion) is f r o m 1 t o 4096. se tt l i n g ti m e or ti m e c o ns t a n t is ch os en b y t h e us er . sa m p l e rat e is the co m b ined sam p le ra te o f al l t h e i n t e rle a v e d c h a n n e ls co m i ng in t o t h e a g c/half-ban d in ter p o l a t ed f i l t er s. i f tw o cha n n e ls a r e b e i n g us e d to p r o c es s o n e c a r r i er o f u m t s a t 2 c h i p r a t e , t h en eac h c h a n ne l w o rks a t 3.84 mh z and t h e c omb i n e d s a m p l e r a te c o m i ng i n to t h e ha l f - b and i n te r p ol a t e d f i l t e r s i s 7 les in t h e p r e v io us e q ua t i on, if ha lf-b a n d i n t e r p ol a t ing f i l t ers a r e les i n t o f t h e sig n al ga in wi t h a n d q d a ta en t e ri n g th e a g c secti o n . t h i s s i gn al the p r o d uc ts o f t h e ga i n m u l t i p lier a r e t h e a g c s c ale d o u t p u t s, g a in fo r t h e n e xt s e t of s a m p les. th e s e r e t r un c a t e d to t h e r e q u ir e d b i t t ope i f f i th e m o 6.02 d b co uld t r s a v a i tr un er r o to a c cas e p e c u a g c y high val u es f o r f i l t er ga in k a n d t h en use ci c decima tio n t o ac hieve a s l o w lo o p . i n this wa y , t o v e d e n h e signal lev e l . i f a v er a g in g o f f o ur al lev e l . a s n lo o p l . s e lec g leve l m o de b y s e t t in g b i t 4 o f th e t e n d ds o f t h e p e ak-t o- a v erag e ra t i o , t h e d e s i re d c l ippi ng l e vel opt i o n pr ov i d e s a w a y to ke e p f r om n q u i c f o r t f i g u l mo d f i rs t, t h e da t a f r o m t h e ga i n m u l t i p lier is t r un c a t e d t o a lo w e r s o l u tio n (4, 5, 6, 7, 8, 10, 12 , o r 16 b i ts) as s e t b y th e a g c c o n t ro l word. a n e r ror te r m ( b ot h i a n d q ) i s ge ne r a te d t h at i s t h e dif f er en ce b e tw e e n t h e sig n als b e fo r e a n d af t e r t r un ca t i o n . t h is t e r m is p a ssed t o t h e co m p lex sq ua r e d magni t ude b l o c k, . 6 8 m s ps. u s e t h is ra te in t h e ca lc u l a t io n o f p o by p a s s e d . the lo o p f i l t er ou t p u t co r r es p o nds t o t h e sig n a l ga in t h a t is u p da te d b y t h e a g c. b e c a us e a l l co m p u t a t ion o f t h e s a m p th e loo p f i l t e r i s d o n e i n log a ri th m i c d o m a i n (t o th e base 2), th e signal ga in is g e n e ra t e d usin g t h e exp o n e n t (p o w er o f 2) o f th e l o op f i lte r output . the ga i n m u l t i p lier g i v e s t h e p r o d uc bo th t h e i ga in is a p plie d a s a co a r s e 4- b i t s c a l in g an d t h e n a f i n e s c a l e 8-b i t m u lt i p lier . ther efo r e , t h e a p plie d sig n al gain is b e t w e e n 0 db an d 96.296 db in s t eps o f 0 . 024 db . i n i t ial val u e f o r sig n al ga in is p r og ra mma b le usin g re g i st er 0x0d fo r a g c a and reg i st er 0x15 f o r a g c b . which ha v e 19 - b i t r e p r es en t a t i o n . th es e a r e in t u r n us e d as i a n d q f o r calcula t in g t h e po w e r a n d a g c er r o r a n d lo o p f i l t er e d t o p r o d uce sig n a l a g c s c ale d o u t p u t s can be p r o g ra mm e d t o ha v e 4-, 5-, 6-, 7-, 8-, 10-, 12-, o r 16-b i t wid t h s usin g t h e a g c con t r o l w o r d (0x0a, 0x12). th e a g c s c ale d o u t p u t s a w i d h s usin g t h e c l i p p i n g cir c ui tr y s h o w n in f i gur e 51. n loop g a in setting l t er ga in k o c c u p i es o n l y on e l s b o r 0 . 0 0 3 9 , th en, d u r i n g u l t i p lica tio n wi th e r r o r t e rm , e r r o r s o f u p t b e unca t e d . this tr un c a tio n is d u e t o t h e lo w e r b i t wid t h l a b l e i n t h e a g c lo o p . i f f i l t er ga in k is t h e maxim u m val u e, ca t e d er r o r s a r e les s tha n 0. 094 db (eq u i v al en t t o 1 ls b o f r t e r m r e p r es en t a t i on). g e n e ral l y , a smal l f i l t er ga in is us e d h i e v e a l a r g e t i me c o n s t a n t l o op ( o r sl ow l o op s ) , but , i n t h i s , i t w o u l d ca us e la rg e er r o rs t o g o un dete c t e d . d u e t o t h is liar ity , t h e desig n ers r e c ommend t h a t , if a us er wan t s slo w l o o p s, th e y s h o u ld use fair l t h e a g c lo o p mak e s la rg e inf r e q uen t gain c h an g e s co m p a r e d sm al l f r eq uen t ga in c h an g e s, as in the case o f a no r m al sm al l- g a i n l o op f i lte r . h o we ve r , t h ou g h t h e a g c l o op m a ke s l a r g e inf r eq uen t ga in c h a n g e s, a s l o w tim e co n s ta n t is s t il l ac h i e a n d t h er e is les s t r un ca t i o n o f e r r o rs. averag e s a mples setting th o u g h i t is com p lic a t e d t o ex p r es s t h e exac t e f fe c t o f t h e n u m b er o f a v era g in g sam p les, thinkin g in t u i t i v e l y , i t has a s m oo th in g e f f e ct o n t h e wa y th e a g c loo p a t ta ck s a s u d d in cr ease o r a s p i k e i n t sa m p le s i s u s ed , th e a g c a t tac k s a s u d d e n in cr e a se in s i gn al lev e l m o r e s l o w ly co m p a r ed t o n o a v er a g ing. th e s a me a p p l i e s t o t h e m a nn er i n which t h e a g c a t t a cks a s u dden de cr e a s e i n th e s i gn desired clipping level mo de o t e d p r ev i o u s l y , ea c h a g c ca n be co n f i g u r ed so th a t th e lo c k s o n t o a d e s i r e d c l i p p i n g lev e l o r a des i r e d sig n al leve t desir e d c l i p p i n individ u al a g c co n t r o l w o r d s (0x0a, 0x12). f o r sig n als tha t t o exce e d t h e b o u n t r u ca t i n g t h os e sig n als a n d s t i l l p r o v ide a n a g c t h a t a t t a c k s k l y and s e t t les to t h e desir e d o u tp u t le vel. t h e sig n a l p a t h h i s mo d e of op e r a t i o n i s s h ow n w i t h bro k e n ar row s i n r e 51, a n d t h e op era t ion is simi la r t o t h e desir e d sig n al le v e e . r e
ad6652 rev. 0 | page 44 of 76 for averaging and decimating the update samples and taking their square root to f mode. in place of the request de ipping level is subtracted, leaving an error term to be proc- der loop filter. the rest of the loop s the desired signal level mode. this vel n recei he aver e ad6652 to update the e rece chan e accurate m o pin coun at the u e, the u chos hannel 0. likewise, the hold-off counter of and number that corresponds to the number of clk cycles that will ic decimated value the proper pin sync pin triggers the agc hold-off counter with a one-shot pulse every time the pin is written high. once triggered, the counter counts a ne note he hold-off dela if the user chooses not to use pin sync signals, the user can use s cont 0x12 n written high, performs an immediate start of date sample. this bit has a one-shot ristic an ot need to respond w logic hi being writte it. use of the sync now bit passes the ag hold-off coun s and performs sync ctions witho elay. ch pin sync logic high initiates a new trigger event for the een reserved for configuring ind rms samp les, as in desired signal level sired signal level, a desired be counted ( a known delay) before a new c is updated. writing a logic high to cl essed by the second-or operates the same way a way, the truncation error is calculated and the agc loop operates to maintain a constant truncation error level. apart from bit 4 of the agc control words, the only register setting changes compared to the desired signal level mode is that the desired clipping level is stored in the agc desired le registers (0x0c, 0x15) instead of the request signal level (as in desired signal level mode). synchronization in i stances where the agc output is connected to a rake ver, a signal from the rake receiver can synchronize t age-and-update section of th average power for agc error calculation and loop filtering. this ext rnal signal synchronizes the agc changes to the rake iver and makes sure that the agc gain word does not ge over a symbol period and, therefore, mor esti ation. the external synchronization signal is connected t one or more of the pin sync pins (a, b, c, or d). synchronization requires the use of an agc hold-off ter. the hold-off counter of agc a shares the pin sync th ser has assigned to ddc processing channel 0. therefor ser must attach the external sync signal to the pin sync en for ddc c agc b shares the pin synch that the user has assigned to ddc processing channel 2. therefore, the user must attach the external sync signal to the pin sync that will be assigned to ddc channel 2. the hold-off counter register, 0x0b and 0x13 for agc a agc b, respectively, must be programmed with a 16-bit down to a value of one and then causes a start of decimation for w update sample. : setting the hold-off count to zero disables t counter. setting the hold-off count to one provides the smallest y. the ync now command through the microport. each agc rol register has a sync now bit in registers 0x0a:3 and :3 that, whe decimation for a new up characte d does n to be reset in order to a ne gh n to by c ter fun ut d ea hold-off counter unless first sync only of the agcs control register (bit 1) is set to logic high. when high, only the first sync signal is recognized and any others disregarded until first sync only is reset. along with updating a new decimation value, the cic filter accumulator can be reset if the init on sync bit (bit 2) of the agc control register is set. init on sync is triggered by either sync signal, pin sync, or sync now. addresses 0x0a to 0x11 have b agc a, and addresses 0x12 to 0x19 have been reserved for configuring agc b. the register specifications are detailed in table 29.
ad6652 rev. 0 | page 45 of 76 st (bist) self- hich is intended to test the integrity of the high speed ain s feature provides a simple pass/fail test, which gives el ram is operational. follow these est: t at , the 3-bi data mem user-configurable built-in self-te the ad6652 includes two built-in test features to test the integrity of each channel. the first is a ram bist (built-in test), w random access memory within the ad6652. the second is channel bist, which is designed to test the integrity of the m signal paths of the ad6652. the bist functions are independ- ent of each other and can be operated simultaneously. ram bist use the ram bist to validate functionality of the on-chip ram. thi confidence that the chann steps to perform this t 1. put the channels to be tested into sleep mode via the external address register 0x01. 2. program the ram bist enable bit in the rcf register 0xa8 of the channel address registers to logic high. wai least 1600 clock cycles, then perform step 3. 3. read back register 0xa8 (see table 19). if bit 0 is high test is not yet complete. if bit 0 is low, the test is complete and bits 1 and 2 indicate the condition of the internal ram. if bit 1 is high, then cmem is bad. if bit 2 is high, then dmem is bad. table 19. bist register 0xa8 t data coefficient mem xx1 test incomplete test incomplete 000 pass pass 010 fail pass 100 pass fail 110 fail fail channel bist the channel bist is a thorough test of the selected a d6652 un to tly. nel 0 in sleep mode. 2. configure the channels to be tested as required for the application. this might require setting the nco parameters, the decimation rates, scalars, and rcf coefficients. 3. program the start hold-off counter, 0x83, to a value of 1 in the channel address registers of the channels to be tested. 4. program channel address registers 0xa5 and 0xa6 to all 0s for the channels to be tested. 5. enable the channel bist located at 0xa7 by programming bits 19C0 to the number of rcf outputs to observe. 6. for external address register 5:3C0, program the desired sync ch bits to logic high to select which channels will receive a start soft-sync signal. 7. external address register 5:4 should be programmed high to emit a one-shot soft sync pulse for the start function. 8. reset external address register 5:6 to 0 to allow user- provided test vectors. the internal pseudorandom number generator can also be selected to generate a pn data input sequence by setting bit 7 high. 9. for external address register 5, an internal negative full- scale sine wave is output at the nco frequency, when bit 6 is set to 1 and bit 7 is cleared. 10. when the soft_sync control register is written with the above parameters, the selected channels become active with the programmed attributes. 11. if the user is providing external vectors, then the chip can be brought out of sleep mode by one of the other methods. 12. after a sufficient amount of time, the channel bist signature registers 0xa5 and 0xa6 contain a numeric value that can be compared to the expected value for a known good ad6652 with the exact same configuration. if the values are the same, then there is a very low probability of an error in the channel. note: to better visualize these instructions, see figure 53, sync control block diagram; table 22, the external memory map; and table 24, the channel address registers memory map. signal path. with this test mode enabled, it is possible to use externally supplied test vectors or an internal pseudonoise (pn) data generator. an error signature register in the rcf monitors the output data of the channel and is used to determine if the proper data exits the rcf. if errors are detected, then each internal block can be bypassed and another test can be r debug the fault. the i and q paths are tested independen follow these steps to perform this test: 1. place the channel(s) to be programmed in sleep mode at external address 3:3C0. set the appropriate bits high. example 3:0 = 1 places chan
ad6652 rev. 0 | page 46 of 76 p synchroniz a tion d a t e d u s i n g t h e ve r s a t i l e s o f t -sy n c and p i n-sy n c sig n als no r m al l y as s o cia t ed wi t h d g s e c t ion s . th e sy n c hr oniz a t ion is m s h a d ca n i a t h e micro p o r t), o r a p i n_ s y n c (via an y o f th e f o ur ad6652 s y n c p i n s a, b , c, an d f fo r a cha nnel/ c h i the ad6652 has been desig n e d t o easil y syn c hr o n ize tw o c o m mon f u nc t i ons : st a r t an d ho p . w h i l e t h e a g c s t a g e can a l s o b e s y nch r o n i z e d , it i s not a c c o m m o ad6652 sy n c hro n iza t ion. st a r t an d ho p f u n c t i o n s a r e des c r i b e in det a i l i n t h e fol l o w in acco p lish e d w i t h t h e us e o f a shado w r e g i ster a n d a h o ld -o f f co un t e r . s e e f i g u r e 52 f o r a sim p lif i ed s c h e ma tic o f th e n c o o w r e g i ste r and nc o f r e q u e nc y hol d -of f c o u n te r to un d e r s t a n d b a sic o p era t io n. t r igg e r i n g o f th e ho ld-o f f co un t e r o c c u r wi t h ei t h er a s o f t _s y n c (v d ) . i gur e 53 det a ils h o w sy n c hr o n iza t io n sig n a l s a r e ma na g e d s i n g le r e cei v e p r o c es sing cha n n e l. register readback tc enb nco hop hold-off counter q0 nco shadow register q31 d0 q0 nco frequency register d0 d31 q31 soft sync pin sync from 0x85 and 0x86 nco frequency i0 to nco phase accumulator 32 32 d31 d0 d15 clk preload inputs from 0x84 from tc of start hold-off counter 03198- 0- 039 f i gure 52. nc o sh a d o w r e g i s t er and ho ld- o ff counter ther e a r e tw o t y p e s o f syn c hr oniza t ion s t i m u l i t o ch o o s e f r o m : so ft_ s y n c and pi n_s y n c . th e f i rst m e t h o d is ini t ia t e d o v er t h e m i c r op or t or s e r i a l pro g r a m m i ng p o r t u s i n g a s o f t w a re rout i n e. t h e seco nd m e t h o d r e lies o n a n ext e r n al s t im ul us tha t is a t t a c h e d to on e of t h e f o u r s y nc h r on i z a t i o n i n put pi ns ( s y n c a, b , c, a n d d). i n bo th cases, a logic high tr igg e r s th e sy n c hr o - niza tio n p r o c ess. b o th m e t h o d s ca n be use d sim u l t an e o us l y b y s e t t i n g t h e a p p r o p r i a t e q u al if iers. st art s t a r t r e f e r s t o th e s t a r t u p o f an in divid u al c h a n n e l o r c h i p , o r m u l t i p le chi p s. i f a c h a n n e l is no t used , i t sh o u ld b e p l ac ed in s l eep m o de t o r e d u ce p o w e r dissi p a t io n. f o l l o w in g a ha r d r e set (lo w p u ls e o n the ad6652 res e t p i n), al l c h a n n e ls a r e p l aced in s l eep m o de . cha n n e ls can al so be m a n u al l y p l ace d in s l eep s g le h e st a r t l u e is 0, t h is defe a t s t h e st a r t f u n c t i o n , a n d t h e o n t r o l s e c t io n). wh at h a p p e n s i f a sta r t _ s y n c pu ls e is r e cei v e d whi l e t h e cha n n e l is a w a k e (ac t i v e l y p r o c es sin g da t a )? this ca n ac t u al ly b e a v e r y us ef u l to ol to d y na mi ca l l y ad j u st t h e r c f phas e o r timin g t o al lo w syn c hr o n iza t ion o f m u l t i p le ad6652 i c s. ref e r t o t h e dis c us sio n s o f reg i st ers 0x83 a n d 0x a1 in t h e chann e l a ddr ess reg i st e r (car) s e c t io n fo r f u r t h e r expla n a t ion. start with no sync i f no s y nch r on i z a t i o n i s ne e d e d to st ar t m u lt ipl e ch an nel s or m u l t i p le ad665 2s, us e t h e fol l o w i n g m e t h o d t o ini t iali ze t h e de vice: 1. t o p r ogra m a cha n n e l , p u t i t in s l eep m o de (b i t high, e x t e r n al a ddr ess 3:3C0), th en lo ad al l a p p r o p r i a t e co n t r o l an d me mor y re g i ste r s to s e t up t h e prop e r c h a n ne l co nf igura t io n. 2. l o ad t h e st a r t hold-o f f co un ter (0x83) wi t h a 1 6 -b i t va l u e f r o m 1 t o 2 16 ? 1. 3. s e t t h e c h a n ne l s s l eep b i t lo w (e xt er nal a ddr ess 3:3C0). a w ak en i n g f r o m s l ee p in v o l v es a n in t e rn all y g e n e ra t e d s t a r t co m m a n d th a t pe rf o r m s th e sa m e fun c ti o n s a s a so ft w a r e - g en e r a t ed syn c p u lse . t h i s a c ti va t e s t h e c h a n n e l a f t e r t h e h o ld-of f co un t e r r e aches a val u e o f o n e wi t h t h e n e w l y p r o g r a m m ed o r p r ev i o u s pa r a m e t e r s . m o de b y wr i t ing t o t h e r e g i st er co n t r o l l in g t h e s l e e p f u n c t i on, e x t e r n al a ddr ess 3:3C0. b e f o re an d af te r a st ar t c o m m a n d i s re c e ive d by one or more chan nel s , t h e fol l o w ing o c c u rs : 1. j u s t bef o r e the sta r t co m m a n d is is s u ed , wh il e the c h a n n e l i in s l e e p m o de , a n y or a l l c o n t ro l re g i ste r s , i n clu d i n g f i l t e r co ef f i cien ts, can be s a f e l y r e p r og ra m m e d wi t h o u t cras hin th e a d 6 6 5 2 o r cr ea tin g u n wa n t ed o u t p u t . 2. wh e n a st a r t _ s y n c p u ls e is r e ce i v e d , i t t r a n sfers t h e co n t e n ts o f t h e cha n n e l s s t a r t hold-o f f r e g i s t er , 0x83, t o t h e c o un ter s p r elo a d in p u ts and c ommenc es c o un t i n g . w h e n t h e co u n t r e aches a va l u e o f o n e, t h e c h a n n e l i s a w a k en e d a n d ini t ia li ze d wi t h t h e info r m a t io n f r o m e a ch a p plicab r e g i s t e r f o r a p r o p er cha n n e l s t a r t u p . h o w e v e r , if t p r elo a d va ch an nel re ma i n s d o r m an t . no t e t h a t s t a r t d o e s no t a f fe c t t h e a g c h o ld-o f f co un t e r . the co un t e r can be t r igg e r e d o n l y b y set t in g t h e sy nc n o w b i t o r b y p i n sy n c sig n als (s ee t h e a u t o ma t i c gain c
ad6652 rev. 0 | page 47 of 76 channel 0 start sync multiplexer channel 0 hop sync hop ext add 5:5 soft sync0 ext add 5:0 select lines from nco control register t o s t a r t h o l d - o f f c o u n d e x t a d d 4 : 5 select lines from nco control register t o n c o h o l d - o f f c o u n t 03198-0-040 n o te t h at m u lt ipl e q u a lif i e rs a r e r e qui r ed to e n ab l e multiplexer start ext add 5:4 soft sync0 ext add 5:0 t e r e r start sync enable, 0x82:0 and ext add 4:4 a n c b syncc syncd 0x88:8 0x88:7 h o p s y n c e n a b l e , 0 x 8 2 : 1 a n synca syncb syncc syncd 0x88:8 0x88:7 pin sync_en b* pin sync_en c* pin sync_en d* syncb pin syncc pin syncd pin * from external memory address register 4:3-0 note: all circuitry and signals are identical and repeated for each channel except soft syncx. soft syncx control signals are assigned to a single channel and are not shared with any other channel. f i g u re 53. sy nch r o n iz ing s i g n a l r o ut i n g e x amp l e , ch an nel 0 ; eit h er a pin _ sy nc or a s o f t _sy n c sig n al to be r o uted start with soft sync the ad6652 inc l udes th e ab il i t y t o syn c hr o n ize c h a n n e ls o r c h ip s u s i n g t h e m i c r op or t . o n e a c t i on to s y nc h r on i z e i s t h e s t a r t o f cha nne l s o r chi p s. the st a r t u p da te h o ld-o f f co un t e r (0x83) in co n j u n c t ion wi t h t h e s t a r t b i t and sy nc b i t (e xt er nal a ddr ess 5) a l lo ws t h is sy n c hr oniz a t ion. th e st a r t u p da te h o l d - o f f co un t e r de l a ys t h e s t a r t o f a cha n n e l b y t h e 16-b i t val u e p r og ra mm e d a t 0x83 (n um ber of ad6652 cl k p e r i o d s u s e t h e fol l o w in g m e m u l t i p le r e set to th e s y n c s y pin sync_en a * synca pin ad6652 hardware and software sync control for one processing channel to a hop o r st a r t ho ld- o f f counte r ) . t h o d t o sy n c hro n i z e t h e s t a r t o f c h a n n e ls via m i cr o p r o ces s o r co n t r o l: 1. p l ace t h e c h anne ls in s l eep m o de (a ha r d ad6652 res e t p i n fo r c es a l l fo ur dd c p r o c essin g c h a n n e ls in t o s l e e p m o de). ? 1. i f th e c h i p o r c h a n n e l s ha v e n o t been co m p lete l y p r ogra m m e d , wr i t e all o t h e r r e g i s t er s n o w . e c l o c k e d a t n t a g e o us t o do s o in t h e a p plica t ion. the t i m e f r o m when t h e dt a c k 2. w r i t e t h e s t a r t h o ld-o f f co un t e r(s) (0x83) t o a val u e f r o m 1 to 2 16 3. w r i t e t h e s t a r t b i t an d t h e a p pl ica b le chann e l s y n c b i t(s) high a t e x t e r n al a ddr es s 5. this tr igg e r s th e s t ar t h o ld-o f f co un t e rs t o beg i n their co un t. th e co u n t e rs a r wi t h t h e ad665 2 clk sig n al . w h e n i t r e ach e s a co un t o f o n e , t h e s l e e p b i ts o f t h e s e le c t e d cha n ne ls a r e s e t lo w t o t u r n o n t h e channe l wi t h t h e ne w o r exis t i ng o p era t i n g pa ra m e t e r s . n o t e : e a ch c h anne l has a r e d u ndan t s o f t -sy n c co n t r o l r e g i s t e r a ddr ess 0x 81. t h is r e g i ster mi mic s t h e p r o g r a mmin g as s e t in t h e e x t e r n al m e m o r y a ddr es s 5 : 5C4. the us er c a n con t r o l t h e s o f t -sy n c f u n c tio n o f a d d c c h a nne l b y wr i t ing t o th e 0x81 r e g i st er , if i t is a d v a p i n go es hig h ( w hich ack n o w le dges t da t a ) to h e r e ce i p t o f t h e s o f t sy n c co m m a n d when t h e dd c cha n n e l b e g i n s p r o c es sin g da t a is e q ual t o t h e tim e p e r i o d set u p b y th e s t a r t h o ld-o f f co un t e r val u e a t 0x83 pl u s s i x clk c y cl es .
ad6652 rev. 0 | page 48 of 76 c plished with the following method. refer to figure 53 to assist in following this process. 1. place the channels to be programmed in sleep mode. the ad6652 reset start with pin sync the ad6652 provides four sync pins. a, b, c, and d, which are used for very accurate channel synchronization. each ddc channel can be programmed to respond to any or all four syn pins. synchronization of start with one of the external sync pins is accom pin places all four ddc processing channels in sleep mode when toggled low momentarily. 2. write the start hold-off counter(s) (0x83) to a value from 1 to 2 16 ? 1. if the chip or channels have not been completely programmed, write all other registers now. 3. set the start_en bit high (external address 4:4) and choose which pin sync_en bits (external address 4:3C0) are to be used. write the bit high to enable it. 4. set the sync input select bits for each active channel . this is done at address 0x88:8C7. table 20 is the truth table for these b its. table 20. truth table 0x88:8 0x88:7 sync pin selected 0 0 a 0 1 b 1 0 c 1 1 d after programming is complete and when the external si attached to the selected sync p gnal in goes high, this triggers the start r -off counter unless first sync only , s 4:6 is set to logic high. when high, only the ed at pin nco sync the ad6652 includes the ability to synchronize a change in nco frequency o g the microport. the nc er (0x84) in onjunction with the hop bit and the sync bit (external ddress 4) allows this synchronization. basically, the nco equency hold-off counter delays the new frequency from being loaded into the nco by its value (number of ad6652 clks). use the following method to synchronize a hop in frequency of multiple channels via microprocessor control: 1. write the nco frequency hold-off counter (0x84) to the appropriate value (greater than 0 and less then 2 16 ). 2. write the nco frequency register(s), 0x85 and 0x86, to the new desired frequency. 3. write the hop bit and the applicable channel sync bit(s) high at external address 5. this triggers the frequency hold-off counter(s) to begin their count. the counters are clocked with the ad6652 clk signal. when it reaches a c cy data is the working register of channels do not need to at s the programming as set in :5C4. the user can control the hold-off counter of the chosen channel(s). the hold-off counte begins counting using the ad6652 clk signal. when it reaches a count of 1, the sleep bit of the selected channel(s) is set low to awaken the channel(s). each pin sync logic high initiates a new trigger event for the hold external addres first sync signal is recognized and any others are disregard until first sync only is reset. note: each channel has a redundant pin-sync control register address 0x82. this register mimics the programming as set in external memory address 4:6C4. the user can control the sync function of a ddc channel by writing to registers 0x82 and 0x88:8C7, if it is advantageous to do so in the application. the time from when the pin sync goes high to when the ddc channel resumes processing is equal to the time period set up by the start hold-off counter value at 0x83 plus 3 clk cycles. hop hop is a change from one nco frequency to a new frequency. this can apply to a single channel or multiple channels and can be synchronized via microprocessor control (soft sync) or an external sync signal (pin sync), as described in the following sections. awakening the channel from sleep mode generates an internal start command that performs both hop and start functions as if a soft-sync or pin-sync had been received. hop with soft f multiple channels or chips usin o frequency hold-off count c a fr ount of 1, the new frequen transferred from the shadow register to the nco. unlike the start function, the be placed in sleep mode to achieve a frequency hop. note: each channel has a redundant soft-sync control register address 0x81. this register mimic the external memory address 5 soft-sync function of a ddc channel by writing to the 0x81 register, if it is advantageous to do so in the application. the time from when the dtack pin goes high (which acknowledges the receipt of the soft sync command data) to when the ddc channel begins processing data is equal to th time period set up by the frequency or hop e hold-off counter value at 0x84 plus 7 clk cycles.
ad6652 rev. 0 | page 49 of 76 in the start function, the ad6652 provides four sync l rite the nco frequency hold-off counter(s) (0x84) to the 16 he hop on pin sync bit high and the appropriate sync enable high at external address 4. k c logic high initiates a new or the hold-off counter unless first sync only, set. unlike the start function, the laced in sleep mode to achieve a r at a ddc channel by writing to the 0x82 and t is advantageous to do so in the m when the external signal on the sync input pin goes high to when the nco begins processing data is equal to the time period set up by the nco frequency hold-off counter (0x84) plus five master clock cycles. hop with pin sync just as pins, a, b, c, and d, which are used for very accurate channe synchronization. each ddc channel can be programmed to respond to any or all four sync pins. synchronization of hop with one of the external sync pins is described as follows: 1. w appropriate value (greater than 0 and less than 2 ). 2. write the nco frequency register(s), 0x85 and 0x86, to the new desired frequency. 3. set t pin 4. set the sync input select bits for each active channel . this is done at address 0x88:8C7. the truth table for these bits is the same as for the start with pin sync, in table 20. when the selected sync pin is sampled high by the ad6652 clk, this enables the count-down of the nco frequency hold-off counter. the counter is clocked with the ad6652 cl signal. when it reaches a count of 1, the new frequency is loaded into the nco. each pin syn trigger event f external address 4:6 is set to logic high. when high, only the first sync signal is recognized and any others are disregarded until first sync only is re channels do not need to be p frequency hop. note: each channel has a redundant pin-sync control registe address 0x82. this register mimics the programming as set in external memory address 4:6C4. the user can control the pin sync function of 0x88:8C7 registers, if i application. the time fro
ad6652 rev. 0 | page 50 of 76 u t p u t p o r t s r t s t p a r a l l e l o the ad6652 inco r p o r a t es tw o in dep e n d en t 16-b i t p a ral l e l p o fo r o u t p u t da t a t r a n sfer . t o minimi ze p a cka g e b a l l co un t, t h e eig h t l s bs o f e a ch 16- b i t p o r t a r e s h a r e d wi t h t h eir r e s p e c t i v e ds p lin k p o r t da ta b i ts (see f i gur e 54). t h is m e a n s tha t a n o u t p u t p o r t can tra n sm i t 16 -b i t p a ral l e l da ta o r 8-b i t lin k p o r da ta , b u t n o t bo th . t r a n s m i t ti n g bo th link a n d p a ralle l da ta sim u l t an eo us l y r e q u ir es tha t t h e s e con d ad66 52 o u t p u t p o r t b e co nf igur ed f o r tha t p u r p ose . a d 6 6 5 2 p o r t (shared pins) 8 a link port a clock out link port a clock in pclk link port a data or 8 lsb's of parallel port a data / a d 6 6 5 2 p o r t pclk parallel port b msb data parallel port b ack parallel port b req p a channel indicator t a o r 8 l s b ' s of parallel port b data (shared pins) / 8 / 8 nel a ? i n te r p o l a t e d , i n t e r l e a ve d, a n d r a g c mo d i f i e d c h an nel b da ta be ou t p u t o n an y p o r t (s). a p o r t ca n p u t c k m a s t er/s l a v e m o de (descr ibe d in h e s n l i ther p a ral l e l p o r t c o n t r o l reg i s t er 0 x 1a (p o r t a) a n d 0x1c (p o r t b). cha n n e l m o de p r o v ides tw o da ta f o r m a t s. e a c h f o r m a t r e q u ir es a dif f er en t n u m b er o f p a ral l e l p o r t clo c k (pclk) c y cles t o co m p le t e t h e tra n s f e r o f d a t a . i n ea c h ca s e , ea ch da t a e l em en t is t r a n sfer r e d d u r i n g o n e pcl k c y cle . s e e f i gur e 55 a n d f i gur e 5 6 , which p r es en t cha n n e l m o de p a ral l e l p o r t t i ming. the 16- b i t in t e rle da t a fo r e a ch is te a ta i s o n th e b u s . q da ta is o u t p u t d u ri n g th e s u b s e q u e n t pclk c y c l e; th e p a i q a n d pb i q o u t p u t in dica t o r p i n s a r e lo w d u r i n this c y c l e . parallel port a msb data parallel port a ack parallel port a req parallel port a channel indicator parallel port a i and q indicator / 8 / 2 b link port b clock out link port b clock in l i n k p o r t b d a r a l l e l p o r t b / 2 parallel port b i and q indicator 03198-0-041 f i gure 54. o u tput p o r t c o nf igur ation e a c h p a ral l e l o u t p u t p o r t has six da t a so ur ces r o u t ed t o i t (se e th e f u n c ti o n al b l oc k di a g ra m i n f i g u r e 1): ? n o ni n t er p o l a t e d r a m co ef f i ci en t fir f i l t er o u t p u t da t a f r o m cha n n e ls 1, 2, 3, a n d 4 ? i n te r p o l a t e d , i n t e r l e a ve d, a n d / or a g c mo d i f i e d c h an da ta / o an y o f th e six s o ur ces ca n be co nf igur e d to o u t p u t p a ral l el da ta o r ds p link da ta . ou t p o r t co n t r o l r e g i s t ers ( t a b le 29) p e r f o r m t h es e m u l t i p lexin g and s e lec t io n t a sks. p a ra l l e l p o r t co nf igura t io n is sp e c if ie d b y acce ssin g p o r t c o n t r o l reg i st er a ddr es s e s 0 x 1 a an d 0x1c f o r p a ral l e l p o r t s a a n d b , r e s p ec t i ve l y . p o r t c l o t h e m a st er/s l a ve pclk m o des s e c t io n) is co nf igur e d usin g t p o r t c l o c k co n t r o l r e gis t er a t a d dr es s 0x1e. n o te tha t t o ac c e s t h es e r e g i s t ers, b i t 5 (acces s p o r t co n t r o l r e g i s t ers) o f e x t e r n al a ddr es s 3 (s le e p r e g i s t er) m u st b e s e t. th e addr es s is t h e se lec t e d b y p r ogra m m i n g t h e car r e gis t er a t e x t e r n al a ddr ess 6. the p a ral l e l p o r t s a r e ena b le d b y s e t t in g bi t 7 of t h e lin k co n t r o r e g i s t ers a t a ddr es s e s 0x1b a n d 0x1d f o r p o r t s a an d b , r e s p ec ti v e l y . e a ch p a ral l e l p o r t is ca p a b l e o f o p era t in g i n e cha n n e l m o de or a g c mo de. t h es e mo des a r e des c r i b e d i n d e ta il in t h e f o llo w i n g sectio n s . channel mode p a ral l e l p o r t c h a nne l m o de is s e lec t e d b y set t ing b i t 0 o f a ddr es s e s 0x1b a n d 0x1d f o r p a ral l e l p o r t s a and b , r e s p ec - t i vely . i n ch an nel m o d e , i and q wo rds f r o m e a ch chan nel are d i r e ct ed t o th e pa rall e l po r t , b y pa s s i n g th e a g c . t h e s p ec i f i c c h a n n e ls o u t p u t b y th e p o r t a r e se lec t e d b y set t in g b i ts 1C4 o f a v e d fo r m a t pr o v ides i a n d q o u t p u t sa m p le o n back-t o-bac k pclk c y c l es. b o th i an d q w o r d s co n s is t o f th e f u l l p o r t wid t h o f 16 b i ts. d a ta o u t p u t t r ig ger e d o n t h e r i sin g e d ge o f pclk w h en b o t h req a n d a c k a r e as s e r t e d . i da t a is ou t p u t d u r i n g t h e f i rs t p c lk c y cle; t h e p a i q a n d pbi q o u t p u t i n di ca tor p i n s a r e s e t h i g h to i n di c a th a t i d g
ad6652 rev. 0 | page 51 of 76 pclkn pxreq pxiq pxch[1:0] t dpp i[15:0] q[15:0] t dpiq pxch[1:0] = channel # t dpch pxack px[15:0] t dpreq 03198-0-042 f i gure 55. channel mode i n t e rleav e d f o rmat the 8-b i t con c ur r e n t f o r m a t p r o v ides 8 b i ts o f i da ta and 8 b i ts o f q da t a sim u l t a n eo us l y d u r i ng o n e pclk c y cle , also tr igg e r e d o n the r i sin g edg e o f pclk. the i b y t e o c c u p i es th e m o s t sig n if ica n t b y t e o f t h e p o r t , whi l e t h e q b y te o c c u p i es t h e le as t n if ica n t b y t e . the p a i q and pbi q o u t p u t i n dic a t o r p i ns a r e t h i g h d u r i n g th e pclk c y c l e . n o t e tha t if da t a f r o m m u l t i p le c h a n n e ls is o u t p u t co n s ec u t i v e l y , th e p a i q and p b i q o u t p u t indic a t o r p i n s r e ma in hig h u n t i l da ta f r o m al l cha n n e ls has been output . ag c m o d e sig s e pxch[1:0] pclkn t dpreq pxreq pxack t dpp px[15:0] i[15:8] q[7:0] pxiq t dpiq pxch[1:0] = channel # t dpch 03198-0-043 f i g u re 56. cha nne l m o de 8i/ 8 q p a r a l l e l f o r m at t h e p a ch[1:0] a n d p b ch[1:0] p i n s p r o v ide a 2-b i t b i n a r y val u e i n di ca t i n g t h e s o ur ce channe l o f t h e da t a c u r r en t l y b e in g output . c a r e s h o u ld b e tak e n t o r e ad da ta f r o m the p o r t as so o n as p o s s i b le . i f n o t, t h e s a m p le wi l l b e o v er wr i t t e n when t h e n e xt new da ta s a m p l e a r r i v e s. t h is o c c u r s o n a p e r - cha n n e l b a sis; t h a t is, a c h an nel 0 s a m p le is o v er wr i t te n o n ly b y a ne w cha n n e l 0 s a m p le , a n d s o o n . t h e o r der o f da ta o u t p u t is dep e n d en t o n w h en da ta a r r i v e d a t th e po r t , wh i c h i s a fu n c ti o n o f t o tal d e cim a t i o n ra t e , s t a r t h o ld - of f v a lu e s , and s o on . pr i o r i t y or d e r i s , f r om h i g h e s t to l o we st , cha n n e ls 0, 1, 2, a n d 3. e l s . ag c a a c c e p t s d a t a f r o m d t o r e d s u c h t n e r a t i on of output s a m p l e s f r om ann e ls is o u t o h as e (b y typ i cal l y 180). e a c h p a ral l e l n p r o v i d e da ei t h er o n e o r b o t h a g cs. b i t 1 and f reg i st er a d d s e s 0x1 a (p o r t a) an d 0x1c (p o r t b) l t h e i n c l u s i on f d a t a f r om a g c s a a n d b , re sp e c t i v e ly . o de p r o v ides on ly o n e i & q fo r m a t , w h i c h is simi lar to - bit i n te r l e a ve o r m a t of c h an nel mo d e . w h e n b o t h r e q k a r e a s s e r t e h e n e x t r i si n g edg e o f pclk tr igg e r s the of a 1 6 - bit a g c i word f o r one p c l k c y c l e. t h e p a iq a n d pb i q o u t p u t in dica t o r p i ns a r e high d u r i ng this c y c l e , a n d are l o w ot he r w i s e. a 1 6 - bit a g c q word i s prov i d e d d u r i ng t h e s u b s e q u en t p c lk c y cle . i f t h e a g c ga in w o rd has b e en u p da te d sin c e t h e last s a m p le , a 12- b i t r s s i w o r d is p r o v ide d d u r i n g t h e p c l k c y c l e f o l l ow i n g t h e q wo rd of 1 2 m s b s of t h e p a r a l l el p o r t da t a pin s . this rss i w o r d is t h e b i t-i n v e rs e o f t h e sig n a l ga in w o r d use d in t h e ga in m u l t i p lier o f th e a g c. t h e d a t a p r o v ided b y th e p a ch[1:0] a n d pb ch[1:0] p i n s in a g c mo de is di f f er en t t h a n t h a t p r o v ide d in ch a nne l m o de . i n a g c m o d e , p a ch[0] a n d p b ch[0] in d i ca t e t h e a g c so ur ce o f th e da ta c u r r en t l y bein g o u t p u t (0 = a g c a, 1 = a g c b). p a ch[1] a n d pb ch[1] in d i ca te w h et h e r th e cur r en t d a ta is a n i/q w o r d o r a n a g c rss i w o r d (0 = i/q w o r d , 1 = a g c rss i w o r d ). the tw o dif f er en t a g c ou t p u t s a r e sh o w n in f i gur e 57 a n d f i gur e 58. p a ral l e l p o r t c h a nne l m o de is s e lec t e d b y c l ea r i n g b i t 0 o f a ddr es s e s 0x1a a n d 0x1c f o r p a ral l e l p o r t s a and b , r e s p ec - ti v e l y . i a n d q da ta o u t p u t in a g c m o d e a r e o u t p u t f r o m th e ag c , n o t t h e i n d i v i d u a l c h a n n c h an nel 0 to c h an nel 3 , w h i l e a g c b a c c e pt s d a t a f r om cha n n e l 2 and cha n n e l 3. e a ch p a ir o f c h a n ne ls is r e q u ir e b e c o n f i g u h a t t h e ge th e c h f p p o r t ca t a f r o m b i t 2 o r es c o n t ro o a g c m t h e 1 6 d f a n d a c d , t output pclkn pxreq pxack px[15:0] pxiq pxch[1:0] t dpreq t dpp i[15:0] q[15:0] t dpiq pxch[0] = agc # pxch[1] = 0 t dpch 03198-0-044 f i gure 57. a g c w i th no rssi w o r d
ad6652 rev. 0 | page 52 of 76 pclkn t dpreq pxreq pxack t dpp px[15:0] i[15:0] q[15:0] pxiq p x c h [ 1 : 0 ] pxch[0] = agc # pxch[1] = 0 rssi[11:0] pxch[0] = agc # pxch[1] = 1 t dpiq t dpch 03198- 0- 045 f i g u re 58. a g c w i t h r ssi w o r d a ve pclk m o des e p a ral l e s l a v e m o de . th e de is s e t s 0x1e). h e pa rall e r t s po w e r u p i n s l a v e m o d e t o a v o i d pos s i b l e n t en ti o n s n th e p c l k p i n . n m a s t er m de, pclk is an o u t p u t w h ose f r eq uen c y is the l o k f r eq uen c y divide d b y th e p c lk divis o r . b e ca us e l u es fo r pclk_divis o r [2:1] ca n ran g e f r o m 0 t o 3, in t e ger o rs o f 2, 4,o r 8, r e s p ec ti v e l y , ca n be ob tain e d . b e c a us e t h e u m c h es t ck r a t e in mas o de is e lec t e d b y s e t t in g b i t 0 o f a d dr es s 0x1e. n sla v e mo e , e x t e r n al cir c ui t r y p r o v ides t h e p c lk sig n al. l a v e-m o de p c lk sig n als can be ei t h er sy n c hro n o u s o r n chr o n o s . the max i m u m sla v e- m o de pc lk f r e q uen c y is z. p a r a llel port pin f u nc tions n a ti v e t o th e ad6652 clk. this p i n p o w e rs u p as a n in p u t t o a v o i d p o s s ib le co n t en tio n s. ot h e r p o r t o u t p u t s a n g e o n t h e r i sin g edg e o f pclk. req a c t i ve hig h o u tp u t , sy n c hr on ous to pclk. a l o g i c hig h o n t h i s s t h a t da t a i s a v ai l a bl e to b e shi f te d ou t of t h e p o r t . gi c h i g i g h un til al l p e nding da ta ha s been te d out k h i g ro nou s i n put . a p ply i ng a l o g i c l o w on t h i s h i b i t el p o r t d a t a shif t i ng. a p ply i ng a lo g i c hig h to p i n w h i s h i g h c a us es th e p a ral l e l p o r t t o s h if t o u t acco r m e d d a ta m o d e . p x a c k i s p l e d o l l i n g e d ge of p c l k . d a t a i s sh i f te d out on t h e i sin g f pclk a f t e r pxa c k is sam p led . pxa c k c a n e l d hig l y . i n t h is cas e , w h en da ta be co m e s i la b l e , s s 1 pclk c y c l e a f t e r th e as ser t io n o f q ( s ee f i gur e 58). h w h e n e n t o n t h e p o r t o u t p u t , o t h e r w is e . h [ 1 : 0 : 0 ] e s e p i n s a ta i n b o th d a ta m o d e s . i n c h a n n e l de , t h es i t b i na r y n u m b er iden t i f y in g t h e r ce cha t da t a w o r d . i n a g c m o de , [0] i c a t e s t = a g c a, 1 = a g c b), a n d [1] t e s w is i/q da t a (0) o r a ga i n d (1). 1 5 : 0 ] , l e l o u t s. c o n t en ts and f o r m a t a r e m o de- e n d e n t. master/sl t h l p o r t s o p era t e i n ei t h er mas t er o r m o v i a t h e p o r t clo c k con t r o l r e g i s t er (a ddr e s t l po co o i o ad6652 c c va divis 1 , maxim l l o c k ra t e o f t h e ad6652 is 65 mh z, th e hig t er m o de is also 65 mh z. m a st er m p s i d s asy u 100 mh pclk i n p u t/o u t p ut. a s an o u t p u t ( m a s ter mo de) , t h e max i m u m fr e q u e n c y i s c l k / n , w h er e cl k is t h e a d 665 2 clo c k an d n is a in teg e r divis o r 1, 2, 4 o r 8. a s a n in p u t (s l a v e mo de), i t mig h t b e asy n c h r o n o us r e l c h pi n i n di c a t e a l o h v a l u e r e m a i n s h s h i f . p x a c a c t i v e h a s y n c h p i n i n s p a r a l l t h i s en r e q da ta d i n g t o th e p r ogra m s a m n t h e f a n e xt r e d g e o be h h co n t in uo us a v a h if t i n g b e g i n r e i gur e 55 t o f paiq, pbiq h i g e v er i da t a is p r es lo w p a c ], pb c h [ 1 t h s e r v e t o i d e n ti f y d m o e p i ns fo r m a 2 - b s o u n n e l o f t h e c u r r e n i n d h e a g c so ur c e ( 0 indic a h et her t h e c u r r en t da t a w o r d w o r p a [ p b [ 1 5:0] p a ral t p u t da ta p o r d e p
ad6652 rev. 0 | page 53 of 76 f e a c h ot he r , o w s ug h reg i st er 0x1d . link port the ad6652 has tw o co nf igura b le lin k p o r t s tha t p r o v ide a s e a m les s da ta in t e r f ace wi th t h e t i g e rs h a r c t s -101 s e r i es ds p . e a c h link p o r t al lo ws th e ad6652 t o wr i t e o u t p u t da t a t o t h e r e ce i v e d m a cha n n e l in t h e t i g e rs h a r c fo r t r a n sfer t o me mor y . b e c a u s e t h e y op e r a t e i n d e p e nd e n t l y o eac h lin k p o r t c a n be co nn ec t e d t o a dif f er en t t i g e rs h a r c o r dif f er en t lin k p o r t s o n t h e s a me t i g e rs h a r c . f i gur e 59 s h h o w t o co nn ec t o n e o f t h e tw o ad6652 lin k p o r t s t o o n e o f t h e fo ur t i g e rs h a r c lin k p o r t s. l i nk p o r t a is conf igur e d t h r o reg i st er 0x1b and l i n k p o r t b is co nf igur e d t h r o ug h ad6652 lclkin lclkout ldat pclk tigersharc lclkin lclkout ldat pclk 8 03198-0-046 f i gure 59. link p o r t c o nn ec tion b e t w e e n ad6652 and t i g e rs har c link port d a t a forma t e a c h lin k p o r t c a n o u t p u t da t a to th e t i g e rs h a r c in f i ve dif f er en t fo r m a t s: 2-cha n n e l, 4-cha n n e l, de dic a te d a g c, re d u n d an t a g c w i t h re c e iv e s i g n a l st re ng t h i n d i c a tor ( r s s i ) word, an d re d u n d a n t a g c w i t h out r s si word. e a ch f o r m a t o u t p u t s tw o b y tes o f i da t a and tw o b y t e s o f q da t a t o fo r m a 4-b y t e i q p a ir . b e ca us e t h e t i gers h a r c li nk p o r t t r a n sfers da t a in q u ad-w o r d ( 16-b y t e ) b l o c ks, f o ur i q p a ir s ca n m a k e u p o n e q u ad-w o r d . i f t h e c h ann e l da t a is se lec t e d (b i t 0 = 0 o f 0x1b/ 0x1d), th en 4-b y t e i q w o r d s o f th e f o ur c h a n n e ls ca n be o u t p u in succession, or a l t e r n a t in g ch a nne l p a ir i q t wo r d s ca n b e o u t p u t . f i gur e 60 a n d f i gur e 61 s h o w t h e q u ad-w o r d tra n s- m i t t e d f o r eac h cas e wi th co r r esp o ndin g reg i s t er val u es f o r co nf igur in g e a ch lin k p o r t . link port a or b ch 0 i, q (4 bytes) ch 1 i, q (4 bytes) ch 2 i, q (4 bytes) ch 3 i, q (4 bytes) a d d r 0 x 1 b o r 0 x 1 d b i t 0 = c ch 0 i, q 0 , b i t 1 = 0 ( 4 b y t e s ) (4 bytes) ch 1 i, q (4 bytes) r t b c ( 4 , q ) 03198- 0- 047 o m r c f u t p u t t wi th t h u r ed t o o t da t a f r o e s a m e d r d s (b i t 2 tw o b y t e s (12 b i ts a p p e n d e d wi t h 4 0s), s o th e link p o r t s e n d s d t o m a k e a f u l l 16-b y t e q u ad-wo r d . link port a h 0 i , q b y t e s ) ch 1 i, q ( 4 l i n k p o h 2 i , q ch 3 i, q ch 2 i, q c h 3 i b y t e s ) (4 bytes) (4 bytes) ( 4 b y t e s addr 0x1b and 0x1d bit 0 = 0, bit 1 = 1 f i gure 60. link p o r t d a t a f r i f a g c o i s s e lec t e d (b i t 0 = 1), th en rss i inf o r m a t io n ca n b e s e n e i q p a ir f r o m ea c h a g c. e a c h l i nk p o r t can be co nf i g u t p u t da t a f r o m o n e a g c, o r bo th lin k p o r t s c a n o u t p u m the sam e a g c. i f bo th link p o r t s a r e tra n sm i t - t i n g t h a t a , th e n r s s i i n f o rm a t i o n m u s t be s e n t w i th th e i q w o = 0 ) . n o t e tha t t h e ac t u a l rss i w o r d is o n l y tw o b y t e s o f 0s im m e dia t e l y a f ter eac h rss i w o r n o t e tha t b i t 0 = 1, b i t 1 = 0, a n d b i t 2 = 1 is n o t a valid co nf igura t io n. bi t 2 m u st b e set t o 0, t o o u t p u t a g c a i q and rss i w o r d s o n link p o r t a an d a g c b i q and rss i w o r d s o n link p o r t b . link port a or b addr 0x1b or 0x1d bit 0 = 1, bit 1 = 0, bit 2 = 0 link port a or b addr 0x1b or 0x1d bit 0 = 1, bit 1 = 0, bit 2 = 1 link port a link port b a d d r 0 x 1 b a n d 0 x 1 d b i t 0 = 1 , b i t 1 = 1 , b i t 2 = 0 agc a i, q (4 bytes) agc a rssi (4 bytes) agc a i, q (4 bytes) agc a rssi (4 bytes) agc b i, q (4 bytes) agc b rssi (4 bytes) agc b i, q (4 bytes) agc b rssi (4 bytes) agc a i, q (4 bytes) agc b i, q (4 bytes) agc a i, q agc b i, q (4 bytes) (4 bytes) , q agc b rssi (4 bytes) 03198- 0- 048 f i gure 61. link p o r t d a ta fro m a g c n g f r o m t h e ad6652. pcl k ca n be r u n as fas t as 100 mh z in sla v e m o de . let e t r ans m i s s i on of t h e f u l l 1 6 by te s of a t i ge r s h a rc qu a d - w or d. s t o h e n d has h e rc. agc a i, q agc a rssi (4 bytes) a g c b i (4 bytes) (4 bytes) link port t i ming b o th lin k p o r t s r u n o f f o f pclk, which can be ext e r n al l y p r o v ided t o th e c h i p (a ddr ess 0x1e b i t 0 = 0) o r g e n e ra t e d f r o m th e mas t er c l o c k o f th e ad665 2 (a ddr es s 0x1e b i t 0 = 1). t h i s r e g i s t er b o ots t o 0 (s la v e m o de) a n d al lo ws t h e us er t o co n t r o l th e da ta r a t e c o m i the lin k p o r t p r o v ides 1-b y t e da ta w o r d s (l a[7: 0], lb[7:0] p i n s ) an d o u t p u t c l o c ks (la c lk o u t , lb clk o u t p i n s ) in re sp ons e to a re a d y s i g n a l ( l a c l k i n , l b c l k i n pi n s ) f r om t h e r e cei v er . e a c h link p o r t tra n smi t s 8 b i ts o n e a c h edg e o f l c lk o u t , r e quir in g 8 l c l k o u t c y cles t o co m p due t o th e t i g e rs h a r c link p o r t p r o t o c ol , th e ad6652 m u wa i t a t leas t 6 pclk c y c l es a f t e r th e t i g e rs h a r c is r e ad y t r e cei v e da t a , as i n dic a t e d b y t h e t i g e rs h a r c s e t t in g t r e s p ec ti v e ad6 652 l c lki n p i n hig h . on c e t h e ad6652 link p o r t has wa i t e d t h e a p p r o p r i a t e n u m b er o f pclk c y cles a be g u n tra n s m i t t i n g d a t a , th e t i g e rs h a r c d o e s a co nn ecti vi t y c h eck b y s e n d ing th e ad6652 lclk i n lo w a n d th en hig h whil e th e da ta is being tra n smi t t e d . this t e l l s the ad6652 link p o r t t h a t t h e t i g e rsh a rc s d m a i s r e ad y t o r e cei v e t h e n e xt q u a d - w o r d a f t e r com p let i o n o f t h e c u r r en t q u ad-w or d . b e ca us e t co nnec t ivi t y c h ec k is do n e in p a ral l e l t o th e da t a tra n sm is sio n , th e ad6652 c a n s t r e a m unin t e r r u p t ed da ta t o t h e t i g e rs h a d0 d1 d2 d3 d4 d15 d0 d1 d2 n e x t q u a d - w o r d tigersharc ready to receive quad-word wait 6 cycles lclkin tigersharc ready to receive next quad-word lclkout ldat[7:0] 03198- 0- 049 f i g u re 62. link p o r t d a t a t r ans f er
ad6652 rev. 0 | page 54 of 76 i s s i o n i s a 4- b i t t h e li nk p o r t co n t r o l r e g i s t ers (0x1b a n d a n d t h e o u t o f t h e le n g th o f t h e w a i t be f o r e da ta tra n s m p r og ra mma b l e val u e i n 0x1d b i ts 6C3). this val u e al lo ws th e ad6652 p c l k t i g e rs h a r c pclk t o be r u n a t dif f er en t ra t e s a n d phas e. ? ? ? ? ? ? ? ? tsharc lclk ad lclk f f ciel wait _ 6652 _ 6 w a it en s u r e s t h a t t h e am o u n t o f tim e t h e ad6 652 n eeds t o w a i t t o b e gi n da ta tra n s m i s s i o n i s a t lea s t eq u a l t o th e mi n i m u m amou n t of t i me t h e ti ge r s h a r c i s e x p e c t i n g it to w a it . i f t h e pclk o f the a d 6 6 5 2 i s o u t o f p h as e wi t h t h e pclk o f the t i g e rs h a r c a n d th e a r g u m e n t t o th e ce il() fu n c ti o n i s a n i n t e g e r , th en w a it m u s t be s t r i ctl y gr ea t e r th a n th e v a l u e gi v e n in t h e ab o v e fo rm u l a . i f t h e l c lks a r e in phas e , t h en t h e maxi m u m ou t p u t da t a ra te is tsharc lclk ad lclk f f _ 6652 _ 6 15 o t h e r w is e , i t is tsharc lclk ad lclk f f _ 6652 _ 6 14 tigersharc c o nfigur a t ion b e ca us e the ad6652 is al wa ys th e tran sm i t t e r in this lin k and t h e t i g e rs h a rc is alwa ys t h e re cei v er , t h e fol l o w i n g val u e s c a n b e p r og ra mm e d in t o t h e l c tl r e g i st er fo r t h e l i nk p o r t us e d t r e cei v e ad6652 o u t p u t da t a . table 21. tigersharc lctl x register confi g uration r e g i s t e r v a l u e o vere 0 spd user 1 l t e n 0 p s i z e 1 tto e 0 cere 0 lren 1 rtoe 1 1 the term use r m e a n s t h a t t h e a c t u a l regi st er va lue dep e n ds on t h e us er s appl ication.
ad6652 rev. 0 | page 55 of 76 external memory map the external memory map is the only way to gain access to the four channel address register pages and the output port control register page. this set of eight registers is shown in table 22. these registers are collectively referred to as the external memory map registers, because they control all accesses to the channel address space as well as output control registers. the use of each of these individual registers is described in detail in the following sections. it should be noted that the serial control interface has the same memory map as the microport interface and can carry out exactly the same functions, although at a slower rate. table 22. external memory map address name comment 7 access control register (acr) 7: auto increment 6: broadcast 5C2: instruction[3:0] 1C0: a[9:8] 6 channel address registers (car) 7C0: a[7:0] 5 soft_sync control register (write only) 7: pn_en 6: test_mux_select 5: hop 4: start 3: sync ch3 2: sync ch2 1: sync ch1 0: sync ch0 4 pin_sync control register (write only) 7: reserved write to logic low 6: first sync only 5: hop_en 4: start_en 3: pin sync_en d 2: pin sync_en c 1: pin sync_en b 0: pin sync_en a 3 sleep (write on ly) 7C6: reserved write to logic low 5: access output port control registers 4: reserved low 3: sleep ch3 2: sleep ch2 1: sleep ch1 0: sleep ch 0 2 data register 2 (dr2) 7C4: reserved 3C0: d[19:16] 1 data register 1 (dr1) 15C8: d[15:8] 0 data register 0 (dr0) 7C0: d[7:0]
ad6652 rev. 0 | page 56 of 76 e microport or serial port. , it 6 of the register is the broadcast bit, which determines how n bits 5C2, which n[3:0]), are ch ] pins. the instruction that s the chip_id ss. this ws up to 16 chips t the same port and ory mapped with allows the me serial port of a h t processor to configure up to 16 chips. the broadcast bit is h h, the instruction[3:0] word allows ultiple ad6652 chan els and/or chips to be configured ultaneously indepe 3:0] pins. the ossible instruction eful smart antenna syst ls listening to gle antenna or car ltaneously. xs in the commen ent dont s in the digital de t is enabled (bit 6 h) readback is n otential for ternal bus contentio erefore, if readback is subsequently ed, the broadcast t should be set low. its 1C0 of the acr ar address bits that decode which of the ur channels are bein sed. if the instruction bits decode n access to multiple c nnels, then these bits are ignored. if the struction decodes an ccess to a subset of chips, then the bits otherwise d the channel being accessed. instructions, ruction comm access control register (acr) external address 7 the acr specifies certain programming characteristics such as autoincrement or broadcast, which are to be applied to the incoming instructions, and selects which channel(s) are to be programmed by th bit 7 of this register is the autoincrement bit. if this bit is a 1 then the car register, described in the channel address register (car) section, increments its value after every access to the channel. this allows blocks of address space such as coefficient memory to be initialized more efficiently. b bits 5C2 are interpreted. if broadcast is 0 the are referred to as instruction bits (instructio compared with the ip_id[3:0 matche [3:0] pins determines the acce allo o be connected to mem out external logic. this also sa os if ig m n sim ndent of the chip_id[ 10 p s are defined in table 23. this is us for ems, where multiple channe a sin rier can be configured simu the t portion of the table repres care et hig coding. when broadcas ecause of the p s ot valid b in n. th desir bi b e fo g acces a ha in a a[9:8] etermine table 23. microport inst 7:5C2 ent 0000 all chips and all ls have access. channe 0001 channe 0, 1, 2 of all chips have access. ls 0010 channe ps have access. ls 1, 2, 3 of all chi 0100 all chips get the access. 1 100 0 all chip xxx0 have access. 1 s with chip _id[3:0] = 100 1 all chip xx1 have access. 1 s with chip_id[3:0] = x 110 0 all chip id[3:0] = xx00 have access. 1 s with chip_ 110 1 all chip _id[3:0] = xx01 have access. 1 s with chip 1110 all chip ip_id[3:0] = xx10 have access. 1 s with ch 1111 all chip xx11 have access. 1 s with chip_id[3:0] = 1 a[9: 8] bits control which c . f a channel register autoincrement bit of the the by er gister also contains bist (built-in self-test) commands that turn internal test signals off or on, namely, pseudonoise and negative full-scale e wav d 6, explained below. bits 0C3 soft_sync channel enable bits for each he fou h to one or all of e bits selects the indicated channel(s) to be recipien a sof nchronizing pulsewhenever such signal is erated f this register as described below. a nc be used in addition to a soft-sync signal, if ired. bit 4 is t ng pulse. writing this bit to logic hig ot-type pulse to trigger the start hold-of cted ddc channels according to bits 3C0 nnel/chip synchronization section for furth it also programs channel s reg bit 5 is t op so his bit to logic hig iate hop frequen old-o nnels accordin bits hannel/chip synchro tion s mming this bit also programs the cha addr bit 6 co w the internal input data bus is configured. if this bit is lo the adcs (analogCto-digital converters) are connect the users choice this is n l ope , then the internal gna ll ddc ncos for bist purpose this programmed input choice. ed in bit 7 of this register. if bit 7 ow nal is generated and made av f this bit is high, then the inte al pseudorandom noise generator is enabled and this data is a the internal input data bus. the combined function its 6 and 7 facilitate bist functions. also, in conjunc e misr registers, this allows for detailed in-syste testing. hannel is decoded for access channel address register (car) external address 6 the user writes the 8-bit internal address o to be programmed in the car. if the acr is 1, then this value is incremented after every access to dr0 register, which in turn accesses the location pointed to this address. the channel address register cannot be read back while the broadcast bit is set high. soft_sync control register external address 5 the soft_sync control register is write only. the regist name is somewhat deceiving in that this re sin e, at bits 7 an of this register are the of t r ddc channels. writing a logic hig thes simply ts of t_sync sy gen by bits 4 and 5 o pin-sy signal can des he start software synchronizi h initiates a one-sh f counter of the sele above. see the cha form er in addres ation. programming this b ister 0x82 of each channel. he h ftware synchronizing pulse. writing t h init s a one-shot-type pulse to trigger the cy h ff counter of the selected ddc cha g to 3C0 above. see the c niza ection. progra nnel ess register 0x82 of each channel. nfigures ho w, then ed to ddc ncos according to the orma ration. if this bit is logic high test si ls are connected to a s and overrides any nco the internal test signals are configur is logic l , a negative full-scale sig ailable to the internal data bus. i rn vailable to s of b tion with th m chip
ad6652 rev. 0 | page 57 of 76 pin_sync control register rnal address 4 he write-only n_sync control register. its 3C0 of this register are the pin sync_en control bits. hese bits can be writt o by the controller to select any or all f the external pin syn inputs: a, b, c, and/or d. one pin can e assigned to all channels, one pin can be assigned to one nnel, or any combination in between. this register is fully nfigurable at the channel level (in the channel address register emory map, 0x88) as to which pin-sync signal is selected. a sync signal can be -sync signal, if red. see figure 53. is the start enable h enables tates the routin nal to all the dc channels. this b enables any pin-sync signals that were ted by bits 3C0 ab -1 multiplexer ltimately chosen nc signal that ntrols the start function. see figure 53. programming this bit o programs the cha nel address register 0x82 of each nel. it 5 is the hop enable bit. writing this bit to logic high enables al pin-sync signal to all the n-sync signals that were synchronization signals. if this e o programs the external address 3 e output port control registers memory map. control mode nel. if the w, the ch nel operates n ally. if the bit is high, the icated channel enters a low-p er sleep mode. program- ng this bit als rograms the nnel address register 0x82 ach channel. bit 5 allows access to the output control port registers. when this bit , the gisters are accessed. howeve hen th the output port con egist igh, the value in externa dress mory map for the output c ol po f the normal channel address er m table 29 in the output port control registers bit 6C7 e reserv w. data es s externa ess 2C0 these r rm the data registers dr2, dr1, and dr0, respecti l in ual to or les 0 al address 0 is written to, it triggers ntern 6652 based on the address indicate the a s, during writes to the internal sters, e written last. at t int, d to the internal memory indicate in a[9:0 n the opposite directio once th l address [0] dr0 must be rst d internal access. dr2 is only 4 bits wide. data written to the upper 4 bits of this register are ignored. likewise, reading from this register sed via this same location by e access to or all four r can overwrite the data in 0x80, if ep mode is selected when this bit is written logic exte this is t pi b t en t o c b cha co m pin- used in addition to a soft desi bit 4 r facili bit. writing this bit to logic hig of the external pin-sync sig o g d it selec ove, to be routed to a 4-to be the channels pin-sy and u to co als n chan b or facilitates the routing of the extern ddc channels. this bit enables any pi selected by bits 3C0 above to be routed to a 4-to-1 multiplexer and ultimately chosen to be the channels pin-sync signal that controls the hop function. see figure 53. programming this bit also programs the channel address register 0x82 of each channel. bit 6 is used to ignore repetitive bit is clear, each pin_sync restarts or frequency hops th channel. if this bit is set, then only the first occurrence causes the action to occur. programming this bit als channel address register 0x82 of each channel. bit 7 is reserved; the bits should be written to logic 0. sleep control register in addition to sleep mode control, this register also provides access to th bits 3C0 the sleep of the indicated chan bit is lo an orm ind ow mi o p cha of e bit 4 is reserved and should be written to logic 0. is low channel address re r, w is bit is set high , it allows access to trol r ers. when this bit is set h l ad 6 (car) points to the me ontr rt registers instead o regist emory map. see section. ar ed and should be written lo addr s register l addr egisters fo vely. al ternal data-words have widths that are eq s than 2 bits. when extern an i al access to the ad d in cr and car. thu regi external address [0] dr0 must b his po data is transferre d ]. reads are performed i n. e address is set, externa the fi ata register read to initiate an produces only 4 lsbs. figure 63 is a block diagram of the memory structure. channel address registers (car) 0x00C0x7f: coefficient memory (cmem) this register is the coefficient memory (cmem) used by the rcf. it is memory mapped as 128 words by 20 bits. a second 128 words of ram can be acces writing bit 8 of the rcf control register high at channel address 0xa4. the filter calculated always uses the same coefficients for i and q. by using memory from both of thes 128 blocks, a filter of up to 160 taps can be calculated. multiple filters can be loaded and selected with a single internal the coefficient offset register at channel address 0xa3. 0x80: channel sleep register this register contains the sleep bit for the channel. it mimics the programming of bits 0C3 at external address 3. external address 3 provides simultaneous sleep mode control f ddc channels. the use desired. sle high.
ad6652 rev. 0 | page 58 of 76 n e l 3 p 2 a p u s a r e i d d e n b y b r o a d c a s t f e a t u r e . 0x08 s 1 s 2 d 1 d 4 enb channel decoder* c h a n n e l memory map channel 1 m e m o r y m 2 bits [1:0] of acr, external address 7 c h a n n e l 0 memory map c h a n m e m o r y m a * channel decoder can be output port control registers 20 data bus enb dr2, dr1, dr0, external addresses 2, 1, 0 c c e s s t o o u t p u t c o n t r o l e g i s t e r s , b i t 5 , s l e e p r e g i s t e r , x t e r n a l a d d r e s s 3 0x1e 8 c a r , e x t e r n a l address 6 0x00 input port control registers a d d r e s s b o v e r r a[9:8] from to 03198-0-050 bl ock d i ag r a m of t h e a d 6 6 52 inte en o un t e r a t a d dr es s 0x84 is loaded and beg i ns a l u e o f 1, t h e l a o a d e d w i t h t h e d a t a h en th e s t a r t b i t is , t h e sle e p b i t in a ddr ess 0x8 0 is wr i t t e n lo w i m i cs b i ts 4, 5, an d 6 o f e x t e r n al m e m o r y m a p h e p r og ra mmin g a t e x t e r n al m e m o r y n e ls, t h e us er ca n c u st omi z e a v er wr i t in g t h e da t a i n 0x82.i f t h e ini t ia l b y e x t e r n al a d d r es s 4 is sa tisfac t o r y , the n o t ne e d t o r e p r og ra m t h e e l e m e n ts o f t h is r e g i st er . t h e h o p_en o r the a t i c s tan d in g th e p i n _ s y n c l v s h e 1 6 -b i t val u e i s n b e us e d in t h is wa y t o e so l u ti o n o f th e a d c c k. s f u r t h e r o r m a t io n ab i l t er phas e ad j u st m e n t . i f t h is r e g i st er is it te n to l o g i c h e n t h e s t ar t o c c u rs i mme d i a t ely af te r t h e n c p u lse a r r s. i f i t is wr i t ten t o logic 0, then t h e co un t e r es n o t r e sp ond to a s y nc p u ls e. 8 6 . this is kn o w n as a f i g u re 63. rna l m e m o r y m a ps and co nt r o ls 0x81: soft_ s ync register t h i s r e gi s t e r i s u s ed t o i n i t i a t e so ft w a r e - g en e r a t ed s y n c ev en ts t h r o ug h t h e mic r o p o r t. i t mimic s t h e p r o g r a mm ing o f bi ts 4 a n d 5 a t e x t e r n al a ddr es s 5. i f t h e h o p b i t is wr i t t e n hig h , th th e h o p h o ld-o f f c t o co un t do wn. w h en t h e co u n t r e ach e s a v ch an nel s nc o f r e q u e nc y a c c u m u tor i s l f r o m cha n n e l a ddr es s e s 0x85 and 0x86. w wr it te n hi g h , t h e st ar t hol d - o f f c o u n te r i s l o ade d w i t h t h e v a lu e a t a ddr ess 0x 83 a n d b e g i ns to c o un t do w n . w h en t h e co un t r e ach e s a v a l u e o f 1 an d t h e ch an n e l i s st ar te d. 0x82: pin_ sync register t h is r e gis t er m a ddr ess 4. b e c a us e t a ddr ess 4 a p pli e s t o al l fo ur ch a n p a r t ic u l a r cha n n e l b y o p r ogra m m i n g p r o v id e d us er do e s u n li k e the tw o b i ts in 0x81 abo v e , s e t t in g s t a r t_en (b i t s 1 a n d 0) o f this r e gis t er d o es no t tri g g e r a n yth i n g . th e s e b i ts si m p ly al lo w , o r ena b le , a n ext e r n al sy n c hr o n izi n g s i g n a l to b e rout e d to t h e ch an n e l s st ar t an d / or hop m u lt i - plexers. e v en t h o u g h a sig n al has b e en enab le d t o r e ach t h e m u lt ip l e x e r , it s t i l l ne e d s t o b e s e lec t e d . t h is job is acco m p lished b y b i ts 8 a n d 7 o f 0x88, as dis c us s e d be lo w . the s c h e m d i a g ra m o f f i gur e 53 is h e l p f u l in u n d e r ena b lin g an d s e l e c t io n b i t s o f t h e in v o e d r e g i st ers. b i t 2 o f 0x82 en ga g e s th e f i rs t s y n c o n l y f u n c tio n fo r th e c h a n n e l . this b i t is a co p y o f e x t e r n al a d d r es s 4 , b i t 6, b u t c a n be o v er wr i t t e n to c h a n g e the p r ogra m m i n g o f a p a r t ic ula r chan nel. i f t h is b i t is cl e a r , e a ch pi n_s y nc rest ar ts o r reho p th e c h ann e l . i f t h is b i t is set, t h en o n l y the f i r s t syn c p u lse ca uses th e a c ti o n t o occu r . 0x83: start ho ld-off counter t h e s t a r t h o ld-o f f co un t e r is loaded wi th t wr i t t e n t o t h is addr ess. w h en t h e s t a r t f u n c t i on is t r ig g e r e d b y ei t h er a s o f t _s y n c o r p i n_s y nc, t h e h o ld-o f f co un t e r b e g i n s de cr em e n t i n g . w h en t h e co u n t r e ach e s a v a l u e o f o n e , t h e c h an nel i s brou g h t out of sl e e p mo d e a n d b e g i n s pro c e s s i ng da ta . i f the c h a n nel i s alr e ad y r u n n i ng , the pha s e o f the f i lte r ( s ) a d j u s t ed s u c h t h a t m u l t i p l e ad66 52 s c a n be s y n c h r o n ize d . a p e r i o d ic p u ls e o n t h e s y n c p i n c a a d j u s t t h e tim i n g o f th e f i l t e r s wi th t h e r s a m p l e c l o e e t h e 0xa1 r e g i st er des c r i p t io n fo r i n f o u t f w r 1 , t s y i v e d o 0x84: hop or frequency ho ld-off counter t h e n c o fr e q u e n c y h o l d - o ff c o u n t e r i s l o a d e d w i th th e 1 6 - b i t val u e wr i t t e n t o t h is addr ess u p o n r e cei p t o f ei t h er a s o f t _s ync o r p i n_s y n c . t h e co un t e r b e g i n s co un t i n g , and w h en the co un t r e ach e s a va l u e o f 1, t h e 3 2 -b i t nc o f r e q uen c y w o r d i s u p da ted wi th t h e val u es a t 0x85 a n d 0 x h o p o r h o p_s y n c . w r i t in g this r e g i s t er t o a va l u e o f 1 ca us es t h e n c o f r e q ue n c y t o b e u p da te d imme dia t e l y when t h e s y nc co m e s in t o t h e c h a n n e l . i f i t is wr i t t e n t o a 0, t h en n o h o p o c c u r s . n c o h o ps ca n be ei t h er p h ase-co n t in uo us o r n o n - phas e-con t i n uous, dep e ndin g u p o n t h e st a t e o f b i t 3 o f t h e
ad6652 rev. 0 | page 59 of 76 the sync occurs. if this bit is high, then the phase not updated to the working register until the channel is either brought out of sleep es a value of 1. if the frequency cy as the shadow is written. memory map bit wid nco control register at channel address 0x88. when this bit is low, then the phase accumulator of the nco is not cleared, but starts to add the new nco frequency word to the accumulator as soon as accumulator of the nco is cleared to 0, and the new word is then accumulated. 0x85: nco frequency register 0 this register represents the 16 lsbs of the nco frequency word. these bits are shadowed and are mode, or a soft_sync or pin_sync has been issued. in the latter two cases, the register is updated when the frequency table 24. channel address hold-off counter count reach hold-off counter value is set to a value of 1, then the register is updated as soon as the shadow is written. 0x86: nco frequency register 1 this register represents the 16 msbs of the nco frequency word. these bits are shadowed and are not updated to the working register until the channel is either brought out of sleep mode, or a soft_sync or pin_sync has been issued. in the latter two cases, the register is updated only when the frequen hold-off counter count reaches a value of 1. if the frequency hold-off counter is set to a value of 1, then the register is updated as soon channel address register th comments 00C7f coefficient memory (cmem) 20 128 x 20-bit memory 80 channel sleep 1 0: sleep bit from ext_address 3 81 soft_sync control register 2 1: hop 0: start 82 pin_sync control reg ister 3 2: first sync only 1: hop_en 0: start_en 83 start hold-o ff counter 16 start hold-off value 84 nco frequency hold-off counter 16 nco_freq hold-off value 85 nco frequency register 0 16 nco_freq[15:0] 86 nco frequency register 1 16 nco_freq[31:16] 87 nco phase offset register 16 nco_phase[15:0] 88 nco control register 9 [1:0] 8-7: sync input select 00 = a, 01 = b, 10 = c, 11 = d 6: input port select b or a, 0 = a, 1 = b 5-4: reserved, write both bits logic low 3: clear phase accumulator on hop 2: amplitude dither 1: phase dither 0: bypass (a-input -> i-path, b -> q) 89C8f unused 90 rcic2 decimation ? 1 12 m rcic2 ? 1 91 rcic2 interpolation ? 1 9 l rcic2 ? 1 92 rcic2 scale 12 11: reserved, write to logic low 10: reserved, write to logic low :0] 9-5: rcic2 _quiet [4 4-0: rcic2_loud [4:0] 93 reserved 8 d (must be written low) reserve 94 cic5 decimation ? 1 8 m cic5 ? 1 95 cic5 scale 5 4-0: cic5_scale[4:0] 96 reserved 8 reserved (must be written low) 97C9f unused a0 rcf decimation ? 1 8 m rcf ? 1 a1 rcf decimation phase 8 p rcf a2 rcf number of taps ? 1 8 n taps ? 1 a3 rcf coefficient offset 8 co rcf
ad6652 rev. 0 | page 60 of 76 bit wid channel address register th comments a4 rcf control register 11 10: rcf bypass bist 9: rcf input select (own 0, other 1) 8: program ram bank 1/0 7: use common exponent 6: force output scale 5-4: output format nt 12 + 4 1x: floating poi point 8 + 4 01: floating 00: fixed point 3-0: output scale a5 bist signature for i path 16 bist-i a6 bist signature for q path 16 bist-q a7 bist o utputs to accumulate 20 19-0: number of outputs (counter value read) a8 ram bist control register 3 2: d-ram fail/pass pass 1: c-ram fail/ 0: ram bist enable a9 output control register 10 9: map rcf data to bist registers 5: output format 1: 16-bit i and 16-bit q i and 12-bit q 0: 12-bit 4-0: reserved, write to logic 0 0x87: nco phase offset register this register represents a 16-bit phase offset to the nco. it can be interpreted as values rang ing from 0 to just under 2. the o the 16 msbs of the 32-bit nco rrive at the final phase angle number ular 16-bit phase offset is added t phase accumulator to a used to compute the amplitude value. 0x88: nco control register this 9-bit register controls features of the nco and the channel. the bits are defined in this section. for details, see the numerically controlled oscillator section. bits 8C7 of this register choose which one of the four pin_sync pins (a, b, c, or d) is used by the channel to initiate channel start and frequency hop functions. these bits can also be used to make timing adjustments to a channel. table 25 shows the bit logic state needed to select a partic pin_sync. table 25. bit logic states for sync pins 0x88:8 0x88:7 sync pin selected 0 0 a 0 1 b 1 0 c 1 1 d bit 6 of this register defines which adc channel, a or b, is used by the ddc channel being programmed. if this bit is low, then nput port a selected; if this bit is high, input port b is selected. bits 5C4 are reserved and must be written logic low. e m ared. it - equen- e and amplitude dither use of these features is y stage to be bypassed. when this occurs, the data from input port a is th of the channel and the data from input ws a lue ister is the decimation minus one. the rcic2 ecimation can range from 1 to 4096, depending upon the interpolation of the channel. the decimation must always be greater than the interpolation. i bit 3 determines whether or not the phase accumulator of th nco is cleared when a hop occurs. the hop can originate fro either pin_sync or soft_sync. when this bit is set to 0, the hop is phase-continuous and the accumulator is not cle when this bit is set to 1, the accumulator is cleared to 0 before begins accumulating the new frequency word. this is appropri ate when multiple channels are hopping from different fr cies to a common frequency. bits 2C1 control whether or not the phas functions of the nco are activated. the determined by the system constraints. see the numericall controlled oscillator section for more information on the use of dither. as usual, a logic high activates the function. bit 0 of this register allows the nco frequency translation passed down the i pa port b is passed down the q path of the channel. this allo real filter to be performed on baseband i and q data. ox89C0x8f: unused unused. 0x90: rcic2 decimation ? 1 (m rcic2 ? 1) this register sets the decimation in the rcic2 filter. the va written to this reg d
ad6652 rev. 0 | page 61 of 76 suit scalar can be chosen. for ils, see the second ection. 1: rcic2 interpol ) s register is used to ation in the rcic2 fil value written to th inus c2 interpolation can range from 1 to 512, dependin pon the decimation o he rcic2. there is no timing error ciated with this in ils, see the secon cic filter sect c2 scale regist is used to provide attenuation to mpensate for the gai of the rcic2 and to adjust the linea i- zation of the data from the floating-point input. the use of this ale register is influenced by the rcic2 growth. for details, see r, ator, ate for the fth-order cic ? 1) e nus p d be el is synchronized, it retains the phase setting chosen here. this can be used as part of overy loop with an external processor or can al ulti ile using a single rcf p t filter section. 0 f the numbe nus 1 is written to this re er. 0xa3: rcf coeffici t iste tion of the 256-word co t o select among mult to memory and re nced b t iste inter is updated (from the shadow register) on every new filter output sample. this allows the coefficient offset to be written without e with the new filter. sses the rcf filter and sends the cic5 output data to the bist-i and bist-q registers. the 16 msbs of the cic5 data trol controls the source of the input data to the processes the output data of its t processes the data from the an ed to allow multiple rcfs to be used together to . m rcic2 must be chosen larger than l rcic2 , and both must be chosen such that a able rcic2 deta -order rcic filter s 0x9 ation ? 1 (l rcic2 ? 1 thi set the interpol ter. the is register is the interpolation m 1. the rci g u f t asso terpolation. for deta d- order r ion. 0x92: rcic2 scale the rci er co n r sc the second-order rcic filter section. bit 11 is reserved. write all bits to logic 0. bit 10 is reserved. write all bits to logic 0. bits 9C5 are the actual scale value used when the level indicato li pin associated with this channel, is active (logic 1). bits 4C0 are the actual scale value used when the level indic li pin associated with this channel, is inactive (logic 0). 0x93: reserved eight bits, reserved (must be written low). 0x94: cic5 decimation C 1 (m cic5 ? 1) this register is used to set the decimation in the cic5 filter. the 8-bit value written to this register is the decimation minus 1. 0x95: cic5 scale the 5-bit cic5 scale factor is used to compens growth of the cic5 filter. for details, see the fi filter section. 0x96: reserved reserved (must be written low). 0x97C0x9f: unused unused. 0xa0: rcf decimation ? 1 (m rcf this register is used to set the decimation of the rcf stage. th value written to this register is the desired decimation mi one. although this is an 8-bit register that allows decimation u to 256, most filter designs should be limited to between 1 an 32. higher decimations are allowed, but the alias rejection of the rcf might not be acceptable for some applications. 0xa1: rcf decimation phase (p rcf ) this register allows any one of the m rcf phases of the filter to used and can be adjusted dynamically. each time a filter is started, this phase is updated. when a chann a timing rec low m ple rcfs to work together wh air. for det ails, see the ram coefficien xa2: rc number of tap C 1 (n rcf ? 1) r of taps for the rcf filter mi gist ent offset (co rcf ) his reg r is used to specify which sec efficien memory is used for a filter. it can be used t iple filters that are loaded in fere y this pointer. his reg r is shadowed, and the filter po disturbing operation, even while a filter is being computed. th next sample that comes out of the rcf is 0xa4: rcf control register the rcf control register is an 11-bit register that controls the general features of the rcf as well as output formatting. the bits of this register and their functions are described below. bit 10 bypa can be accessed from this register, if bit 9 of the output con register at channel address 0xa9 is set. bit 9 of this register rcf. if this bit is 0, then the rcf own channel. if this bit is 1, then i cic5 of another channel. the cic5 channels that the rcf c be connected to when this bit is 1 are shown in the table 26. these can be us process wider bandwidth channels table 26. rcf input configurations channel rcf input source when bit 9 is 1 0 1 1 0 2 1 3 1 bit 8 is used as an extra address to allow a second block of 128 words of cmem to be addressed by the channel addres at 0x00C0x7f. if this bit is 0, then ses the first 128 words are written; if this bit is 1, then the next 128 words are written. this bit is hosen. these modes are enabled by bits 5 and 4 of this register. when this bit is 0, then the i and q output exponents are determined separately based on their used to program only the coefficient memory so that filters longer than 128 taps can be realized. bit 7 is used to control the output formatting of the ad6652s rcf data. this bit is used only when the 8 + 4 or 12 + 4 floating-point modes are c
ad6652 rev. 0 | page 62 of 76 indivi d u a l ma g n i t udes. w h en t h is b i t is 1, t h e n t h e i and q da t a is a co m p lex f l oa t i n g -p o i n t n u m b er , w h er e i and q us e a sin g l e exp o n e n t t h a t is det e r m i n e d b a s e d o n t h e maxi m u m ma g n i t ude of i or q . b i t 6 is used t o fo r c e th e o u t p u t scale fac t o r in bi ts 3C0 o f this r e g i st er t o b e us e d t o s c ale t h e da t a e v e n w h e n on e o f t h e f l o a t i n g -p o i n t ou t p u t m o des is us e d . i f t h e n u m b er is t o o l a rg e t o r e p r es en t wi t h t h e o u t p u t s c a l e ch os en, t h e n t h e ma n t i s s a s o f t h e i and q da t a cli p do n o t o v er f l o w . n o r m al l y , th e ad6652 det e r m in es t h e exp o n e n t val u e tha t o p tim i zes n u m e r i cal acc u rac y . h o w e v e r , if b i t 6 is s e t, th e val u e s t o r ed in b i ts 3 C 0 is used t o s c o ns i s te n t s c a l i n g a n d a c c u r a r e d ic t a b l e ou t p u t ra n g es. o n . c a l e th e o u t p u t . this en s u r e s c y d u r i ng c o n d it i o ns t h a t w a r r an t p b i ts 5 an d 4 ch o o se th e o u t p u t f o r m a t tin g o p tio n used b y t h e r c f da t a . th e op t i o n s a r e def i ne d i n t h e t a b l e 27 a n d a r e d i scu s sed fu r t h e r i n th e ou t p u t p o r t c o n t r o l r e gi s t e r s s e c t i table 27. output formats bit value output formatting option 1x 12-bit mantissa and 4-bit exponent (12 + 4) 01 8-bit mantissa and 4-bit expone n t (8 + 4) 00 fix e d point mode b i ts 3C0 o f t h is r e g i st er r e p r es en t t h e o u t p u t s c ale fac t o r o f t h e r a c t o r is e q ua l to +72.25 db . t o ld b e s e t hig h . th en 16 b i ts o f i da ta ca n be r e ad th r o u g h t h e m i cr o p o r t i n ei th e r t h e 8 + 4, 0xa6: bist register for q this r e g i st er s e r v es tw o p u r p os es. th e f i rst is t o al lo w t h e co m p le t e fun c tio n ali t y o f th e q da ta p a th in t h e c h a n n e l t o be t e st e d i n t h e syst em. s e e t h e u s er -c o n f i gura b l e b u i l t-i n s e lf- t e st (b is t ) sec t io n f o r f u r t h e r d e ta ils. th e s e c o n d f u n c tio n is t o p r o v i d e a cce s s t o th e q o u t p u t da ta th r o u g h th e m i cr o p o r t . t o acco m p lish t h is, t h e m a p rcf d a t a t o bi s t b i t in t h e rcf c o n t r o l reg i st er 2, 0xa9, s h o u ld b e s e t hig h . th en 16 b i ts o f q da ta ca n be r e ad th r o u g h t h e m i cr o p o r t i n ei th e r t h e 8 + 4, 12 + 4, 12-b i t lin e a r , o r 16-b i t lin e a r o u t p u t m o des. this da ta ca n come f r o m ei t h er t h e fo r m a t t e d r c f o u t p u t o r t h e ci c5 o u t p u t . t h i s 2 0 - bit re g i ste r c o n t ro l s t h e n u m b e r of output s of t h e rc f r m e d . 6 u t p u t s a n d t h en t e r m i n a t e . th e lo ading gin e r u n n in g. f o r d e ta ils l t - t o t e s t th e m e m o r i es of th e ad6652, if g i s t e r p p e d q . n d n r c f . th e s c ale f a c t o r is us e d t o s c ale t h e da t a w h e n t h e o u t p u t fo r m a t is in f i xe d-p o in t mo de or wh e n t h e fo r c e exp o n e n t b i t i s hig h . i f b i ts 3 C 0 a r e r e p r es en t e d b y r c f s c ale , t h e s c aling fac t o in db is g i v e n b y db scale rcf factor scaling ) 2 ( log 20 ) 3 ( 10 ? = f o r a n r c f s c al e o f 0, th e s c aling fac t o r is eq ual t o ?18.06 db; fo r a max i m u m rcf s c a l e o f 1 5 , t h e s c a l ing f 0xa5: bist register for i this r e g i st er s e r v es tw o p u r p os es. th e f i rst is t o al lo w t h e co m p le t e fun c tio n ali t y o f th e i da ta p a th i n t h e c h a n n e l t o be t e st e d i n t h e syst em. s e e t h e u s er -c o n f i gura b l e b u i l t-i n s e lf- t e st ( b ist) s e c t io n fo r det a i l s. the s e cond f u nc t i o n is to p r o v i d e a cce s s t o th e i o u t p u t da ta th r o u g h th e m i cr o p o r t . acco m p lish t h is, t h e m a p rcf d a t a t o bi s t b i t in t h e rcf c o n t r o l reg i st er 2, 0xa9, s h o u 12 + 4, 12-b i t lin e a r , o r 16-b i t lin e a r o u t p u t m o des. this da ta ca n come f r o m ei t h er t h e fo r m a t t e d r c f o u t p u t o r t h e ci c5 o u t p u t . 0xa7: bist outputs to a c cumul a te o r ci c f i l t er t h a t a r e obs e r v e d when a b i st t e st is p e r f o the b i s t sig n a t ur e r e g i st ers a t a ddr ess e s 0xa5 a n d 0 x a obs e r v e t h is n u m b er o f o o f this r e gis t er also s t a r ts th e b i s t en o n u t i l i z ing t h e b i st cir c ui t r y , s e e t h e u s er -c onf i gura b l e b u i in s e l f - t e s t ( b i s t ) s e c t i o n . 0xa8: ram bist control register this 3-b i t r e g i s t er is us e d a f a i l u r e is su sp e c te d. bit 0 of t h is reg i ster is w r i t te n wi t h a 1 when t h e channe l is i n sle e p m o de . th e us er wa i t s fo r 1600 clks, an d th en p o l l s th e b i ts. i f b i t 1 is hig h , th en t h e c m e m f a i l e d th e t e s t ; i f b i t 2 i s h i g h , th e n th e d a t a m e m o r y u s ed b y th e r c f fa iled t h e t e st . 0xa9: ou tpu t c o n t r o l r e b i t 9 o f this r e gis t er al lo ws th e r c f o r ci c5 d a ta t o b e m a t o t h e b i st r e g i st ers a t a d dr ess e s 0xa5 a n d 0x a6. w h e n t h is b i t is 0, t h en t h e b i s t r e g i st er is in sig n a t ur e m o de a n d r e ad y fo r a s e lf-t est t o b e r u n. w h en t h is b i t is 1, t h en t h e ou t p u t d a t a f r o m t h e rcf (a f t er fo r m a t t i n g ) o r f r o m ci c5 da t a i s ma p p e d t o t h es e r e g i st ers and can b e r e ad t h r o ug h t h e mic r o p o r t. b i t 5 d e t e r m in es th e w o r d len g t h used b y t h e p a ral l e l p o r t . i f this b i t is 0, th en the p a ral l e l p o r t uses 12-b i t w o r d s f o r i a n d i f this b i t is 1, t h en t h e p a ral l e l p o r t uses 16-b i t w o r d s f o r i a q . w h e n t h e f i x e d - p o i n t output opt i on i s c h o s e n f r om t h e rc f co n t r o l r e gi s t e r , th en th ese b i t s also se t th e r o un d i n g co rr ectl y i t h e output f o r m a tte r of t h e r c f . b i ts 4C0 a r e r e s e r v ed a n d sh o u l d b e wr i t ten lo w w h en p r o g r a mming.
ad6652 rev. 0 | page 63 of 76 t po ble variou late ures used p trol. dep g on the ode of operation, up to four different signal paths can be onitored with these registers. these features are accessed by etting bit 5 of external address 3 (sleep regi nd then g the car (external address 6) to address the eight cations ava lable. response to these settings is directed to lia input port control registers the i eat npu rt control registers ena rimarily for level con s i ndin nput-re d f e m m s ster) a usin lo i the lia, , lib , and lib pins. t o access the input port registers, the progra gain contro ld be wr ten high. the car is then wri en with the ess to th orrect input port register. ord is 10 bits wide and maps to the 10 msb of the antissa. if the upper 10 bits of input port a are less than o ual to this alue, then the lower threshold s been met. i ormal chip peration, this starts the dwell time counter. if he put signal increases above this value, then t e counter is eloaded an awaits the input to drop back t his level. ord is 10 bits wide and maps to the 10 msb of the antissa. if t e upper 10 bits of input port a re greater th r ual to this alue, then the upper threshold as been met. ormal chip peration, this causes the appro iate li pin (lia lia m l bit shou it tt addr e c 0x00: lower threshold a this w m r eq v ha n n o t in h r d o t 0x01: upper threshold a this w m h a an o eq v h in n o pr or ) to become active. his word sets the time that the input signal must be at or w wer th s deac ed. for the t level d ell time m t be set to a t 1. if set s are disable his is a 20 ster. wh old is met fol ing an ursion in , the dwel e counter i ed and ck cles as long e input is a or below the lower threshold. i e signal eases ab coun eloaded s for the er th old again. in range a control register it 4 determ es the polarity of lia and lia 0x02: dwell time a t belo the lo reshold before the li pin i tivat inpu etector to work, the dw us t leas to 0, the li function d. t -bit regi en the lower thresh low exc to the upper threshold l tim s load begins to count high speed clo cy as th t f th incr ove the lower threshold, the ow ter is r h and wait signal to fall below the l res 0x03: ga b in . i f this bit is lear, then t li signal is high when the up r threshold has een exceed . however, if this bit is set, the li pin is low hen active. his allows maximum flexibility hen using is function it 3 = 0 (re ved). bit 2C0 determines the internal latency of the gain detect function. when the lia, lia c he pe b ed w t w th . b ser pins are made active, they are used to change an attenuator or gain stage. because dc, there is a latency associated with the a e settling of the gain change. this register a delay of the lia, lia typically this is prior to the a dc and with th llows the internal signal to be p wer threshold b is 10 bits wide and maps to the 10 msb of the er 10 bits of input port b are less than or e e, then the lower threshold has been met. in n peration, this starts the dwell time counter. if the al increases above this value, then the counter is aits the input to drop back to this level. 0x05: upper threshold b this w rd is 10 bits wide and maps to the 10 msb of the m . if the upper 10 bits of input port b are greater than or e is value, then the upper threshold has been met. in n ip operation, this causes the appropriate li pin (lib or rogrammed. 0x04: lo this word mantissa. if the upp qual to this valu ormal chip o input sign reloaded and aw o antissa qual to th ormal c h lib ) to become active 0x06: dwell time b d sets the time that the input signal must be at or below t pin is deactivated. for the i e dwell time must be set to at 1. if set to 0, the li functions are disabled. this is a 20-bit . when the lower threshold is met following an into the upper threshold, the dwell time counter is aded and begins to count high speed clock cycles as long as is at or below the lower threshold. if the signal aded and he signal to fall below the lower threshold again. ain range b control register e polarity of lib and lib this wor he lower threshold before the li nput level detector to work, th least register excursion lo the input increases above the lower threshold, the counter is relo waits for t 0x0: g bit 4 determines th . if this bit is h when the upper threshold has , if this bit is set, the li pin is low is allows maximum flexibility when using b (reserved. b etermines the internal latency of the gain detect f . when the lib, lib clear, then the li signal is hig however been exceeded. when active. th this function. it 3 = 0 it 2C0 d unction pins are made active, they are t sed to change an attenuator or gain stage. because t r to the adc, there is a latency associated with t nd with the settling of the gain change. this llows the internal delay of the lib, lib ypically u his is prio he adc a register a signal to b e programmed.
ad6652 rev. 0 | page 64 of 76 table 28. m p for input port control registers ss register wid mments emory ma channel addre bit th co 00 lower threshold a lower threshold for input a 10 9C0: 01 upper threshold a upper threshold for input a 10 9C0: 02 dwell time a 19C0: minimum time below lower threshold a 20 03 gain range a c ontrol ister output polarity lia and lia reg 5 4: 3: (0) reserved 2C0: linearization hold-off register 04 lower th reshold b lower threshold for input b 10 9C0: 05 upper thre shold b upper threshold for input b 10 9C0: 06 dwell time b 20 19C0: minim um time below lower threshold b 07 gain range b control register ity lib and lib 5 4: output polar 3: (0) reserved 2C 0: linearization hold-off register output port c ontrol registers roup o registers is dedicated to data management af dual channels have processed the incoming data. the nage data nterleaving, 2 interpolation, a c functions, t port signment, and output port setu . because the re two outp t ports, a and b, the data must e funneled fr ur channe down to two. these registers a onsible for g the ta directly to the proper outpu ort(s) or uring th ther post-filteri tages (ag nd so on) before the output port is selected o access th output port registers for outpu orts a and , bit f externa ddress 3 (the sleep register) m st be written logic h. the ch nnel address register (car) is t en written wi e address t the correct output port registe ee table 29 for a mplete lis g and brief description of all r isters. 0x07: reserved erved. al its should be written logic low 8: lhb r he acronym for interpolating half-band, with l bei ly accep d symbol for interpolation. this register incl des e interleaving stage as well as the half-band filter stage, as own in fi e 64. these two stages are con olled separa om the fin agc stage, so that they do no et lost amon e merous a c control elements. it 3, the lhb a enable bit, acts as an on/off tch for the terleave st e, half-band filter, and the agc stage. see igure 64. if it 3 is low, the interleave stage is shut down a ents any ation of data to t maining ages. this condition is desirable when the t ree stages are eeded and ower conservation is desired. w en bit 3 is h e interleav tage is active and works to int eave the dat of p to four d c channels according to the tr th table of bi 2 nd bit 1. the data is then propagated to the lhb and agc ages with bypass opportunities included. b h channels are interleaved. the truth for these bits is shown in table 29. when high, directs data from the interleave alf-band filter stage and proceed directly to tage without interpolation. the channel data streams a ey are not filtered or interpolated. the m onfiguration is two times the when bit 0 is low, data from the interleave stage is passed the half-band filter and undergoes a 2 interpolation r t data rate of the half-band is four ti s wo channels can be inter- annels are selected using only bit 1; bit 2 is the lhb b e 0x0a: agc a control register utput word length of the agc. the output 12, or 16 bits wide. the truth table to o ord lengths is given in the table 29 of this register sets the mode of operation for the agc. he agc tracks to maintain the output signal s 1, the agc tracks to maintain a constant rror. see the automatic gain control section for d odes. sed to configure the synchronization of the agc. the cic decimator filter in the agc can be directly synchro- xternally generated signal. when synchronized, the a ple for the agc error calculation a y, the agc gain changes can be synchro- nized to a rake receiver. this g f ter indivi y ma i g outpu as p re a u b om fo ls re resp guidin da t p deto e data through o ng s c, a . t e t p b 5 o l a u hig a h th th o r. s co tin eg 0x00C res l b . 0x0 a control registe lhb is t ng a wide te u th sh gur tr tely fr al t g g th nu g b swi in ag f b nd prev further propag he re st h not n p h igh, th e s erl a u d u t a st its 2 and 1 choose whic table bit 0, the bypass bit, stage to bypass the h the agc s re still interleaved, but th aximum data rate from this c chip rate. through ate. the maximum outpu mes the chip rate. 0x09: lhb b control register ame as lhb a, except that only t leaved. ch nable bit. bits 7C5 define the o word can be 4 to 8, 10, btain different out put w emory map, 0x0a. m bit 4 when this bit is 0, t level; when this bit i clipping e etails about these two m bits 3C1 are u nized to an e gc outputs an update sam nd filtering. this wa
ad6652 rev. 0 | page 65 of 76 ag c p r o c e s s e d d a t a from rcfs channel interleave enable/disable (0x08:3, 0x09:2) bypass ( 0 x 0 8 : 0 , 0 x 0 9 : 0 ) bypass (0x0a:0, 0x12:0) l half-band filter and 2 interpolation to output ports a and b 03198-0-051 f i g u re 64. bl ock d i ag r a m of an a g c s t ag e sh o w ing t h e compon ent s and s i g n a l r o ut ing o p t i ons f a g c a s h a r es the p i n s y n c sig n ed to un t e r r e g i s t er a t a ddr es s 0x0 b c h o o s e s n o t t o us e p i n sy n c s b i t has a one-sho t cha r ac t e r i s t ic a n d do es n o t i c hi g h b e i n g wr i t t e n t o i t . u s e o f t h e sy n c n o w b i t b y p a ss es t h e a g c h o ld-o f f w h en t h is b i t is s e t, t h e cic f i l t er is cle a r e d u m b er o f a v era g i n g and p o le p a ra m e t e r p a r e n t h e ci c f i l t er a n d t h e n c hr o n iz a t ion sig n a l mig h t o c c u r p e r i o d i- t a f i l t e r s i s s t ill r e d u ce d t o a c to st b e p r og ra m m ed wi t h a 16-b i t d b f r o m 0 t o u s e d in s t eps o f 0.024 db . a 12-b i t h b n o t e : t h e h o ld-o f f co un t e r o assig n e d t o d d c p r o c essin g c h a n n e l 0. th er e f o r e , if t h e us er i n te nd s to u s e t h e a g c a s hol d - o f f c o u n te r , t h e u s e r m u st a t tac h t h e exter n al sy n c sign al to th e p i n sy n c t h a t is as d d c cha n ne l 0. t h e h o ld-o f f co f o r a g c a m u st be p r ogra m m e d wi th a 16-b i t n u m b er th a t co r r esp o n d s to t h e desir e d d e l a y b e fo r e a n e w ci c de c i ma te d val u e is u p da t e d. w r i t in g a log i c hig h t o t h e p r op er p i n s y n c p i n tri g g e r s th e a g c h o ld- o f f co u n t e r wi th a r e tri g g e ra b l e o n e - s h o t p u ls e e v er y t i me t h e p i n is wr i t t e n hig h . b i t 3 is t h e sy n c n o w b i t. i f t h e u s e r sig n als, t h e us er ca n us e t h e sy n c no w c o mmand b y p r o g r a m- min g t h is b i t hi g h . this p e r f o r m s a n i m m e di a t e st a r t o f de cima t i o n fo r a ne w u p da t e s a m p le an d ini t ia l i zes t h e a g c, if b i t 2 is s e t. t h i ne e d to b e re s e t i n orde r to re sp ond to a ne w l o g co un t e rs; t h er efo r e , t h e nam e sy n c now . b i t 2 is us e d t o det e r m i n e w h et h e r t h e a g c sho u ld ini t ial i z e o n a sy n c no w o r no t. a n d n e w val u es fo r ci c de cima t i o n , n s a m p les, ci c s c a l e , sig n a l ga in gs, ga in k, a r e lo ade d . w h e n b i t 2 = 0, t h e ab o v e- m e n t ion e d p a ram e t e r s n o t up da te d and t h e ci c f i lter is n o t cle a r e d . i n b o t h c a s e s, a a g c u p da t e s a m p le is o u t p u t f r o m de c i m a tor st ar t s op e r a t i n g towards t h e ne x t outpu t s a m p l e wh en ev e r a sy n c no w oc cu r s . b i t 1 is used t o ign o r e r e p e t i ti v e p i n _ s y n c sign a l s. i n so m e a p plic a t ion s , t h e s y cal l y . i f this b i t is c l ea r , eac h p i n_s y n c r e sy n c hr o n izes the a g c. i f t h is b i t is s e t, o n ly t h e f i rs t sy n c hig h is r e cog n i z e d an d s u cce e d i n g sy n c e v en ts a r e ig n o r e d un t i l bi t 1 is r e s e t. b i t 0 is used t o b y p a s s th e a g c sec t io n , w h en i t is set. th e da f r o m th e in t e r p o l a t in g h a lf- b a n d lo w e r b i t wid t h r e p r es en t a t i o n as s e t b y b i ts 7C5 o f t h e a g c a co n t r o l r e gi s t e r . a tr u n ca ti o n a t th e o u t p u t o f th e a g c acco m p lish es this tas k . 0x0b: agc a hold-off counter t h e a g c a h o ld-o f f co un t e r is lo aded wi th t h e 16-b i t val u e wr it te n to t h i s a ddre s s w h e n sy n c no w i s wr i tte n hi g h or a p i n _ s y n c is r e c e i v ed . i f this r e g i s t er is wr i t t e n to a 0, th e a g c a n n ot b e s y nc h r on i z e d . n o t e : t h e h o ld-o f f co un t e r o f a g c a s h a r es the p i n sy n c assig n e d t o d d c p r o c essin g c h a n n e l 0. th er e f o r e , if t h e us er in t e n d s t o us e a g c a s h o ld-o f f co un t e r , t h e us e r m u st ei t h e r a t tac h t h e exter n al sy n c sign al to th e p i n sy n c t h a t is as sig n e d d d c c h a n ne l 0 o r us e t h e s o f t wa r e -con t r ol le d sy n c no w f u n c tion o f b i t 3 a t 0x0a. t h e h o ld-o f f co un t e r m u n u m b er t h a t cor r esp o n d s t o t h e desir e d de l a y b e fo r e a ne w c i c de cima te d va l u e is u p da te d . w r i t in g a lo g i c hig h to t h e p r o p er pi n s y nc pi n t r i g g e r s t h e a g c ho l d - o f f c o u n te r w i t h a r e t r ig g e ra b l e o n e-sh o t p u ls e e v e r y t i m e t h e p i n i s wr i t t e n hig h . 0x0c: agc a desired l e vel t h is 8-b i t r e g i s t er co n t a i n s the desir e d o u t p u t p o w e r lev e l o r desir e d cli p p i n g le vel, dep e n d i n g o n t h e m o de o f o p er a t io n. t h is desir e d r e q u es t r leve l can be s e t i n ?23.99 db , in steps o f 0.094 db . an 8-b i t b i na r y f l o a tin g -p o i n t r e p r es en t a t i o n i s us e d wi t h a 2- b i t exp o nen t fol l o w e d b y t h e 6-b i t m a n t is s a . the m a n t is s a is in s t eps o f 0.094 db an d t h e exp o n e n t is in 6 . 02 db s t eps. f o r exa m p l e: 10100101 r e p r e s en ts 2 6.02 + 37 0.094 = 15.518 db . 0x0d: agc a signal gain this r e g i st er is us e d t o s e t t h e i n i t ia l va l u e fo r a sig n a l ga i n in t h e ga i n m u l t i p lier . this 12- b i t val u e s e ts t h e ini t ial sig n a l ga in betw een 0 a n d 96.296 db b i n a r y f l oa ti n g -po i n t r e p r e s e n t a ti o n i s u s e d w i th a 4-b i t exp o n e n t fol l o w e d b y t h e 8- b i t ma n t iss a . f o r exa m ple: 011110001001 r e p r es en ts 7 6 . 02 + 137 0.024 = 45.428 db .
ad6652 rev. 0 | page 66 of 76 ers comments table 29. memory map for output port control regist address register bit width 08 lhb a control register 4 3: lhb a enable 1 2C1: lhb a signal interleaving 11 all 4 channels 10 channels 0, 1, 2 01 channels 0, 1 00 channel 0 0: bypas s lhb a 1 09 lhb b control register 3 2: lhb b enable 1 1: lhb b signal int erleaving 1: channels 2, 3 0: channel 2 0: bypas s lhb b 1 0a agc a control register 8 7C5: outpu t word length 111 4 bits 110 5 bits 101 6 bits 100 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4: clippi ng error 1: maintain level of clipping error 0: vel maintain output signal le 3: sync now 2: init on sync 1: first s ync only 0: bypas s 0b agc a hold-off counter 16 15C0: hold- off value 0c agc a desired level 8 7C0: desire d output power level or clipping energy (r parameter) 0d agc a s ignal gain 12 11C0: gs pa rameter 0e agc a loop gai n 8 7C0: k para meter 0f agc a pole location 8 7C-0: p para meter 10 agc a average samples 6 5C 2: scale for cic decimator 1C0: numb er of averaging samples 11 agc a update decimation 12 11C 0: cic de cimation ratio 12 agc b control register 8 7C5: outpu t word length 111 4 bits 110 5 bits 101 6 bits 100 7 bits 011 8 bits 010 10 bits 001 12 bits 000 16 bits 4: clippi ng error 1: maintain level of clipping error 0: maintain output signal level
ad6652 rev. 0 | page 67 of 76 comments address register bit width 3: sync n ow 2: init on sync 1: first s ync only 0: bypas s 13 agc b hold-off counter 16 15C0: hold- off value 14 agc b desired level 8 7C0: desire d output power level or clipping energy (r parameter) 15 agc b signal gain 12 11C0: gs pa rameter 16 agc b loop gain 8 7C0 : k para meter 17 agc b pole location 8 7C0: p para meter 18 agc b average samples 6 5C2 : scale for cic decimator 1C0: number of averaging samples 19 agc b update decimation 12 1 1C0: cic de cimation 1a parallel a control 8 7C6: reserved 5: parall el port data format 1: 8-bit parallel i, q 0: 16-bit interleaved i, q 4: chann el 3 3: chann el 2 2: chann el 1/agc b enable 1: chann el 0/agc a enable 0: agc_ ch select 1: data comes from agcs 0: data comes from channels 1b link a control 8 7: link p ort a enable 6C3: wait 2: no rs si word 1: dont output rssi word 0: output rssi word 1: chann el data interleaved 1: 2-channel mode/separate ab 0: 4-channel mode/ab same port 0: agc_ ch select 1: data comes from agcs 0: data comes from channels 1c parallel b control 8 7C6: reserv ed 5: parall el port data format 1: 8-bit parallel i, q 0: 16-bit interleaved i, q 4: chann el 3 3: chann el 2 2: chann el 1/agc b enable 1: chann el 0/agc a enable 0: agc_ ch select 1: data comes from agcs 0: data comes from channels 1d link b contro l 8 7: link port b enable 6C3: wait 2: no rssi word 1: do not output rssi word 0: output rssi word
ad6652 rev. 0 | page 68 of 76 bit width comments address register 1: channel data interleaved 1: 2-channel mode/separate ab 0: 4-channel mode/ab same port 0: agc_ch select 1: data comes from agcs 0: data comes from channels 1e port clock control 3 2C1: pclk divisor 0: pclk master/slave 2 0: slave 1: master 1 set the lhb a and/or lhb b enable bits to logic low only when the entire block functions functions) are to be shut down. 2 pclk boots as a slave. 0x0e: agc a loop gain this 8-bit register defines the open loop gain k. its value can be set from 0 to 0.996 in steps of 0.0039. this value of k is updated in the agc loop each time the agc is initialized. 0x0f: agc a pole location this 8-bit register defines the open loop filter pole location p. its 0 to 0.996 in steps of 0.0039. this value of o umber of samples to be averaged before ic decimating filter. this number can be ean- o utput word length of the agc. the output word can be 4 to 8, 10, 12, or 16 bits wide. the control register bit representation to obtain different output word lengths is given in table 29. bit 4 of this register sets the mode of operation for the agc. when this bit is 0, the agc tracks to maintain the output signal level; when this bit is 1, the agc tracks to maintain a constant clipping error. see the automatic gain control section for details about these two modes. bits 3C1 are used to configure the synchronization of the agc. the cic decimator filter in the agc can be indirectly synchronized to an externally generated signal. when synchro- nized, the agc outputs an update sample for the agc error calculation and filtering. this way, the agc gain changes can be synchronized to a rake receiver or other external block. note: the hold-off counter of agc b shares the pin sync fore, if the user intends to use the agc bs hold-off counter, the user must attach the external sync signal to the pin sync that will be assigned to ddc channel 2. the hold-off counter must be programmed with a 16-bit number that corresponds to the desired delay before a new cic decimated value is updated. writing a logic high to the proper pin sync pin triggers the agc hold-off counter with a retriggerable one-shot pulse every time the pin is written high. bit 3 is the sync now bit. if the user chooses not to use pin sync signals, the user can use the sync now command by program- ming this bit high. this performs an immediate start of not lize on gain k, and pole parameter p are loaded. when bit 2 = 0, the above-mentioned parameters are not updated and the cic filter is not cleared. in both cases, an agc update sample is output from the cic filter and the decimator starts operating towards the next output sample whenever a sync now occurs. bit 1 is used to ignore repetitive pin_sync signals. in some applications, the synchronization signal might occur periodi- cally. if this bit is clear, each pin_sync resynchronizes the agc. (lhb signal interleaving, lhb filteri ng, and agc value can be set from p is updated in the agc loop each time the agc is initialized. this open loop pole location directly impacts the closed loop pole locations. see the automatic gain control section. 0x10: agc a average samples this 6-bit register contains the scale used for the cic filter and the number of power samples to be averaged before being fed t the cic filter. bits 5C2 define the scale used for the cic filter. bits 1C0 define the n they are sent to the c set between 1 and 4 with 00 meaning one sample and 11 m ing four samples. 0x11: agc a update decimation this 12-bit register sets the agc decimation ratio from 1 t 4096. set an appropriate scaling factor to avoid loss of bits. 0x12: agc b control register bits 7C5 define the o assigned to ddc processing channel 2. there decimation for a new update sample and initializes the agc, if bit 2 is set. this bit has a one-shot characteristic and does need to be reset in order to respond to a new logic high being written to it. use of the sync now bit bypasses the agc hold-off counters; therefore, the name sync now . bit 2 is used to determine whether the agc should initia a sync now or not. when this bit is set, the cic filter is cleared and new values for cic decimation, number of averaging samples, cic scale, signal gain gs,
ad6652 rev. 0 | page 69 of 76 irst sync high is recognized and ed. if this register is written to 0, the onized. sync ddc processing channel 2. therefore, if the user intends to use agc as hold-off counter, the user must either ed to desired delay before a new cic per gger- e every time the pin is written high. this 8-bit register contains the desired output power level or ng on the mode of operation. t r level can be set from 0 db to ?23.99 db binary floating-point representa- by the 6-bit man- and the exponent is in 0101 represents 2 6.02 + 37 0.094 = 15.518 db. e initial value for a signal gain used 12-bit value sets the initial signal db in steps of 0.024 db. a 12-bit inary floating-point representation is used with a 4-bit expo- nent followed by the 8-bit mantissa. for example: 011110001001 represents 7 6.02 + 137 0.024 = 45.428 db. x16: agc b loop gain his 8-bit register is used to define the open loop gain k. its value can be set from 0 to 0.996 in steps of 0.0039. this value of k is updated in the agc loop each time the agc is initialized. 0x17: agc b pole location this 8-bit register is used to define the open loop filter pole location p. its value can be set from 0 to 0.996 in steps of 0.0039. this value of p is updated in the agc loop each time the agc is initialized. this open loop pole location directly impacts the closed loop pole locations as explained in the automatic gain control section. amples tio from 1 to 4096. set an appropriate scaling factor to avoid loss of bits. put through either a parallel port interface or a link ace. when 0x1b, bit 7 = 0, the use of link port a is ps or on parallel port a. when bit 0 = 0, parallel port a outputs data from the rcf according by bits 1C4. when bit 0 = 1, parallel according to the format . it 1 determines if parallel port a bit 2 determines if parallel port a . the order of output depends on the rate of triggers from each agc, which in turn is determined by the decimation rate of the channels feeding it. in channel ine which combination of ut. the output order ived from each channel, tion rate of each channel. be used to determine bit 5 determines the format of the output data words. when bit 5 = 0, parallel port a outputs 16-bit words on its 16-bit bus. this means that i and q data are interleaved, and the iq indicator pin determines whether data on the port is i data or q data. when bit 5 = 1, parallel port a is outputting an 8-bit i word and an 8-bit q word at the same time, and the iq indicator pins are high. 0x1b: link port control a data is output through either a parallel port interface or a link port interface. the link port provides an efficient data link between the ad6652 and a tigersharc dsp and can be enabled by setting 0x1d, bit 7 = 1. if this bit is set, only the f succeeding sync events are ignored until bit 1 is reset. bit 0 is used to bypass the agc section, when it is set. when the agc is bypassed, the output data is the 16 msbs of the 24-bit input data from the half-band filter. 0x13: agc b hold-off counter the agc b hold-off counter is loaded with the 16-bit value written to this address when sync now is written high or a pin_sync signal is receiv agc cannot be synchr note: the ssigned to hold-off counter of agc b shares the pin a attach the external sync signal to the pin sync that is assign ddc channel 2, or use the software-controlled sync now function of bit 3 at 0x12. rogrammed with a 16-bit the hold-off counter must be p er that corresponds to the numb decimated value is updated. writing a logic high to the pro pin sync pin triggers the agc hold-off counter with a retri able one-shot puls 0x14: agc b desired lev el desired clipping level, dependi this desired reques in steps of 0.094 db. an 8-bit tion is used with a 2-bit exponent followed eps of 0.094 db tissa. the mantissa is in st 6.02 db steps. for example: 1010 0x15: agc b signal gain h this register is used to set t this in the gain multiplier. ain between 0 db and 96.296 g b 0 t 0x18: agc b average s this 6-bit register contains the scale used for the cic filter and the number of power samples to be averaged before being fed to the cic filter. bits 5C2 define the scale used for the cic filter. bits 1C0 define the number of samples to be averaged before they are sent to the cic decimating filter. this number can be set between 1 and 4 with bit representation 00 meaning one sample and bit representation 11 meaning four samples. 0x19: agc b update decimation this 12-bit register sets the agc decimation ra 0x1a: parallel port control a data is out t interf por disabled and the use of parallel port a is enabled. the parallel port provides different data modes for interfacing with ds fpgas. bit 0 selects which data is output to the format specified port a outputs the data from the agcs specified by bits 1 and 2 in agc mode, bit 0 = 1 and b rom agc a. can output data f can output data from agc b mode, bit 0 = 0 and bits 1C4 determ utp the four processing channels is o depends on the rate of triggers rece a which is determined by the decim the channel output indicator pins can which data came from which channel.
ad6652 rev. 0 | page 70 of 76 s output on link port a. when rcf according to bits 1 and 2. bit 1 has two different meanings, depending on whether data is coming from the agcs or from the rcfs. when data is coming from the rcfs (bit 0 = 0), bit 1 selects between two and four channel data mode. bit 1 = 1 indicates that link port a transmits rcf iq words alternately from channels 0 and 1. when bit 1 = 1, link port a outputs rcf iq words from each of the four channels in succession: 0, 1, 2, 3. however, when agc data is selected (bit 0 = 1), bit 1 selects the agc data output mode. in this mode, when bit 1 = 1, link port a outputs be n i it 0 = 0), then this rammable delay value for link port a ing frequency and nd the tigersharc link port. k lel t data modes for interfacing with dsps or from the rcf according to the format specified by bits 1C4. when bit 0 = 1, parallel port b outputs the data from the agcs according to the format specified by bits 1 and 2. in agc mode, bit 0 = 1 and bit 1 determines if parallel port b is able to output data from agc a. bit 2 determines if parallel port b is able to output data from agc b. the order of output depends on the rate of triggers from each agc, which in turn is determined by the decimation rate of the channels feeding it. in channel mode, bit 0 = 0 and bits 1C4 determine which combination of the four processing channels is output. the output order depends on the rate of triggers received from each channel, which is determined by the decimation rate of each this means that i and q data are interleaved and the iq indica- tor pin determines whether data on the port is i data or q data. when bit 5 = 1, parallel port b is outputting an 8-bit i word and an 8-bit q word at the same time, and the iq indicator pins are high. 0x1d: link port control b data is output through either a parallel port interface or a link port interface. the link port provides an efficient data link between the ad6652 and a tigersharc dsp and can be enabled by setting 0x1d, bit 7 = 1. bit 0 selects which data is output on link port b. when bit 0 = 0, link port b outputs data from the rcf according to the format specified by bit 1. when bit 0 = 1, link port b outputs the data from the agcs according to the format cif bit 1 com ng from channel data mode. bit 1 = 1 indicates that link port a transmits rcf iq words alternately from channels 0 and 1. when bit 1 = 1, link port b outputs rcf iq words from each of the four channels in succession: 0, 1, 2, 3. however, when agc data is selected (bit 0 = 1), bit 1 selects the agc data output mode. in this mode, when bit 1 = 1, link port b outputs agc b iq and gain words. with this mode, gain words must be included by setting bit 2 = 0. however, if bit 0 = bit 1 = 0, then agc a and b are alternately output on link port b and the inclusion or exclusion of the gain words is determined by bit 2. tp two word quad bit c bits lue for link port b between the time the link port receives a data ready from the receiver and the time it transmits the first data-word. the link port must wait at least six cycles of the receivers clock, so this value allows the user to use clocks of differing frequency and phase for the ad6652 link port and the tigersharc link port. for details on the limitations and relationship of these clocks, see the link port section. bit 0 selects which data i bit 0 = 0, link port a outputs data from the the format specified by bit 1. when bit 0 = 1 , link port a outputs the data from the agcs according to the format specified by agc a iq and gain words. with this mode, gain words must included by setting bit 2 = 0. however, if bit 0 = bit 1 = 0, the agc a and agc b are alternately output on link port a and the inclusion or exclusion of the gain words is determined by bit 2. bit 2 determines if rssi words are included or not in the data output. if bit 1 = 1, bit 2 = 0. because the rssi words are only two bytes long and the iq words are four bytes long, the rss words are padded with zeros to give a full 16-byte tigersharc quad-word. if agc output is not selected (b bit can be any value. bits 6C3 specify the prog between the time the link port receives a data ready from the receiver and the time it transmits the first data-word. the link port must wait at least 6 cycles of the receivers clock, so this value allows the user to use clocks of differ phase for the ad6652 link port a for details on the limitations and relationship of these clocks, see the link port section. 0x1c: parallel port control b data is output through either a parallel port interface or a lin port interface. when 0x1d, bit 7 = 0, the use of link port b is disabled and the use of parallel port b is enabled. the paral port provides differen fpgas. bit 0 selects which data is output on parallel port b. when bit 0 = 0, parallel port b outputs data channel. the channel output indicator pins can be used to determine which data came from which channel. bit 5 determines the format of the output data words. when bit 5 = 0, parallel port b outputs 16-bit words on its 16-bit bus. spe ied by bits 1 and 2. has two different meanings that depend on whether data is ing from the agcs or from the rcfs. when data is comi the rcfs (bit 0 = 0), bit 1 selects between two and four bit 2 determines whether gain words are included in the data ou ut. if bit 1 = 1, bit 2 = 0. because the gain words are only bytes long and the iq words are four bytes long, the gain s are padded with zeros to give a full 16-byte tigersharc -word. if agc output is not selected (bit 0 = 0), then this an be any value. 6C3 specify the programmable delay va
ad6652 rev. 0 | page 71 of 76 0x1e: port clock control bit 0 determines whether pclk is supplied externally by the user or derived internally in the ad6652. if pclk is derived internally from clk (bit 0 = 1), it is output through the pclk pin as a master clock. for most applications, pclk is provided by the user as an input to the ad6652 via the pclk pin. bits 2 and 1 allow the user to divide clk by an integer value to generate pclk (00 = 1, 01 = 2, 10 = 4, 11 = 8). microport control the ad6652 has an 8-bit microprocessor port or microport . the microport interface is a multimode interface that is designed to give flexibility when dealing with the host processor. there are two modes of bus operation: intel nonmultiplexed mode (inm), and motorola nonmultiplexed mode (mnm). the mode is selected based on the host processor and which mode is best suited to that processor. the microport has an 8-bit data bus (d[7:0]), 3-bit address bus (a[2:0]), 3 control pin lines ( cs , ds , or rd , r/ w or wr ), and one status pin ( dtack or rdy). the functionality of the control signals and status line changes slightly depending upon the mode that is chosen. write sequencing writing to an internal location is achieved by first writing the upper two bits of the address to bits 1C0 of the acr (access control register, external address 7). bits 7:2 can be set to select the channel, as indicated above. the car is then written with the lower eight bits of the internal address (the car can be written before the acr, as long as both are written before the internal access). data register 2 (dr2) and data register 1 (dr1) must be written first, because the write to data register dr0 triggers the internal access. data register dr0 must always be the last register written to initiate the internal write. read sequencing reading from the microport is accomplished in the same manner. the internal address is set up the same way as the write. a read from data register dr0 activates the internal read; thus, register dr0 must always be read first to initiate an internal read followed by dr1and dr2. this provides the 8 lsbs of the internal read through the microport (d[7:0]). additional data registers can be read to read the balance of the internal memory. read/write chaining the microport of the ad6652 allows for multiple accesses while cs is held low. ( cs can be tied permanently low, if the micro- port is not shared with additional devices.) the user can access multiple locations by pulsing the wr or rd line and changing the contents of the external 3-bit address bus. external access to the external registers of table 22 is accomplished in one of two modes using the cs , rd , wr , and mode inputs. the access modes are intel nonmultiplexed mode and motorola nonmulti- plexed mode. these modes are controlled by the mode input (mode = 0 for inm, mode = 1 for mnm). cs , rd , and wr control the access type for each mode. intel nonmultiplexed mode (inm) mode must be tied low to operate the ad6652 microprocessor in inm mode. the access type is controlled by the user with the cs , rd ( ds ), and wr (r/ w ) inputs. the rdy ( dtack ) signal is produced by the microport to communicate to the user that an access has been completed. rdy ( dtack ) goes low at the start of the access and is released when the internal cycle is complete. see the timing diagrams for both the read and write modes in the ddc timing diagrams section. motorola nonmultiplexed mode (mnm) mode must be tied high to operate the ad6652 microproces- sor in mnm mode. the access type is controlled by the user with the cs , ds ( rd ), and r/ w ( wr ) inputs. the dtack (rdy) signal is produced by the microport to communicate to the user that an access has been completed. dtack (rdy) goes low when an internal access is complete and then returns high after ds ( rd ) is deasserted. see the timing diagrams for both the read and write modes in the ddc timing diagrams section. microport programming overview the ad6652 uses an indirect addressing scheme. the external memory map (or external registers) is used to access the internal memory maps that are made up of a channel memory map and an output port memory map. the 4-channel memory pages are decoded using a[9:8] given in the external memory register 7 of the access control register (acr). the output port register memory map is selected using bit 5 of external address 3 (sleep register). when this bit is written with a 0, the channel memory map is selected; when this bit is 1, the output port memory map is selected.
ad6652 rev. 0 | page 72 of 76 e ory r0 at address (000). when a write to dr0 is detected, the internal microprocessor port state machine then moves the data in dr2Cdr0 to the internal address pointed to by the address in the channel address register (car) and access control register (acr). ite pseudocode void write_micro(ext_address, int data); main(); { /* this code shows the programming of the nco phase offset register using the write_micro function as defined above. the variable address is the external address a[2:0] and data is the value to be placed in the external interface register. internal address = 0x087 */ // holding registers for nco phase byte wide access data int d1, d0; // nco frequency word (16 bits wide) nco_phase = 0xcbef; // write acr write_micro(7, 0x03 ); // write car write_micro(6, 0x87); // write dr1 with d[15:8] d1 = (nco_phase & 0xff00) >> 8; write_micro(1, d1); // write dr0 with d[7:0] // on this write all data is transferred to the internal address d0 = nco_freq & 0xff; write_micro(0, d0); } // end of main internal read access a read is performed by first writing the channel address register (car) and acr as with a write. the data registers (dr2Cdr0) are then read in the reverse order that they were written. first, the least significant byte of the data (d[7:0]) is read from dr0. on this transaction, the high bytes of the data are moved from e internal address pointed to by the car and acr into the remaining data registers (dr2Cdr1). this data can then be read from the data registers using the appropriate 3-bit addresses. the number of data registers used depends solely on the amount of data to be read or written. any unused bit in a data register should be masked out for a read. read pseudocode int read_micro(ext_address); main(); { /* this code shows the reading of the first rcf coefficient using the read_micro function as defined above. the variable address is the external address a[2..0]. internal address = 0x000 */ // holding registers for the coefficient int d2, d1, d0; // coefficient (20-bits wide) long coefficient; // write acr write_micro(7, 0x00 ); // write car write_micro(6, 0x00); /* read d[7:0] from dr0, all data is moved from the internal registers to the interface registers on this access */ d0 = read_micro(0) & 0xff; // read d[15:8] from dr1 d1 = read_micro(1) & 0xff; // read d[23:16] from dr2 d2 = read_micro(2) & 0x0f; coefficient = d0 + (d1 << 8) + (d2 << 16); } // end of main internal write access up to 20 bits of data (as needed) can be written by the following process. any high order bytes that are needed are written to th corresponding data registers defined in the external mem map 3-bit address space. the least significant byte is then written to d wr th
ad6652 rev. 0 | page 73 of 76 ad6652 receiver applications one cdma2000 if carrier with no external analog filtering code division multiple access depends upon a unique code sequence that modulates the if carrier along with the payload data. this permits multiple signals to be transmitted on the same carrier frequency and successfully separated at the receiver. this technique spreads the spectrum of the initial digital bit stream over a much wider bandwidth. the wideband nature and stringent adjacent channel-filtering requirements of cdma2000 allow the ad6652 to process only one cdma2000 channel. to do this requires the processing power of all four channels operating at maximum speed. two cdma2000 if carriers wi th external analog saw filtering if two cdma2000 carriers are to be processed by the ad6652, prefiltering of the analog signal(s) going to the ad6652 is required. surface acoustic wave (saw) filters are commonly used to reduce the digital signal processing required of the ad6652 filters. this combination permits adequate reduction of the adjacent channel interference as specified for that medium and permits two cdma2000 carriers to be processed using only two ddc channels per carrier. two umts or wcdma if carriers with no external analog saw filtering er requirements of wideband cdma ts, the ad665 ma carrier sing p nels for each carrie f exte al analog filters. aseband i and q processor his application calls for baseband i and q analog signals to be outed individually to the two ad6652 adc inputs. the 12-bit dcs digitize the signals and send the data to all four receive rocessing channels for decimation and filtering. therefore, ach channel is processing the same 12 bits of i data and 12 bits f q data simultaneously. the user can shut down unused hannels as desired. rocessing baseband i and q data requires that each active channels nco and quadrature mixer be bypassed by program- ming of the nco control registers. design guidelines when designing the ad6652 into a system, it is recommended that, before starting design and layout, the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements required for certain pins. 1. the following power-up sequence is recommended for the ad6652. first, ensure that reset applications due to less stringent filt and um 2 can receive two wcd s using the proces ower of two chan r without the use o rn b t r a p e o c p is held logic low. apply avdd (3.0 v) and vdd (2.5 v), allowing them both to settle to nominal values before applying vddio (3.3 v). once vddio (3.3 v) has settled to nominal value, bring reset logic high. last, apply a logic low reset pulse for 30 ns to reset the ad6652 into a known state ready for programming. 2. reset pin: the reset pin must be held logic low during power-up sequencing to ensure that the internal logic starts in a known state. certain registers, noted in the datasheet, are cleared after hardware reset. failure to ensure hardware reset during power-up might result in invalid output until a valid reset is applied. 3. the number format used in this part is twos complement. all input ports and output ports use twos complement data format. the formats for individual internal registers are given in the memory map description of these registers. 4. to enhance microport programming, the dtack (rdy) should be pulled high (to vddio) ended val ull-up nd 5 k. 5. cs pin externally using a pull-up resister. the recomm ue for the p resistor is between 1 k a pin is used as chip select for programming with the microport. it is recommended that the designer not tie this pin low at all times. this pin should ideally be pulled high using a pull-up resistor, and the user can pull it low whenever microport control is required. 6. the output parallel port has one clock cycle overhead for every output sample. so, if data from two agcs with the same data rate are output on one output port in 16-bit interleaved i/q mode along with the agc word, then four clock cycles are required for one sample from each channel/agc: one blank clock cycle, and one clock cycle each for i data, q data, and gain data.
ad6652 rev. 0 | page 74 of 76 7. serial port control and serial data output are not available on this part. 8. broadcast and programming multiple ad6652 parts using the same microport control/data signals does not work for input/output port control registers (addresses 0x00 to 0x1e). if two ad6652 parts have different values for input/output control registers, they cannot share the microport bus (see the microport control section). 9. to optimize adc performance, decouple any system- induced noise from the sensitive adc reference nodes. place the 0.010 f, 0.1 f, and 10 f external decoupling capacitors as close as possible to the ad6652 device?s vref, refta/refba, and reftb/refbb pins. see the adc voltage reference section of the data sheet and the evaluation board schematics, which are available on the ad6652 product page at h t u www.analog.com u t h .
ad6652 rev. 0 | page 75 of 76 ad6652 evaluation board and software the ad6652 evaluation board kit contains a fully populated ad6652 pcb, schematic diagrams, operating software, comprehensive instruction manual, and digital filter design software. users can preview the evaluation board schematic, the software, and the instruction manual on the product web page of the analog devices website. a block diagram of the basic components is shown in figure 65. ad6652 u301 clk clk clk fpga u401 32k fifo u501 xtal oscillator u201 j201 external clk input j205 j206 j202 input a j203 input b t201 t202 analog input microport control lines u203 prom buffer u601 j101 6v power supply connector pc parallel printer port connector (j601) j605 8-bit link port b j604 8-bit link port a j602 16-bit parallel output port a j603 16-bit parallel output port b 03198-0-056 figure 65. simplified block diagram of ad6652 pcb
ad6652 rev. 0 | page 76 of 76 outline dimensions 1.00 bsc a b c d e f g h j k l m n p r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 15.00 bsc sq a1 corner index area 16 t seating plane 0.20 max coplanarit detail a 0.70 0.60 0.50 ball diameter 0.50 0.30 17.00 bsc sq top view ball a1 indicator detail a 1.85* 1.71 1.40 compliant to jedec standards mo-192-aaf-1 except for (*) dimensions 1.31* 1.21 1.10 figure 66. 256-lead chip scale ball grid array [cspbga] (bc-256-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad6652bbc ?40c to +85c 256-lead cspbga (chip scale ball grid array) bc-256-2 ad6652bc/pcb evaluation board with ad6652 and software ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03198?0?7/04(0)

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